參數(shù)資料
型號(hào)： CYV15G0204TRB
廠商： Cypress Semiconductor Corp.
英文描述： Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer
中文描述： 獨(dú)立時(shí)鐘的HOTLink二⑩雙串行解串器和雙時(shí)鐘重計(jì)
文件頁(yè)數(shù)： 15/31頁(yè)
文件大?。?/td> 389K
代理商： CYV15G0204TRB
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 15 of 31
Reclocker
Each receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The data is retimed
by the recovered clock and then passed to an output register.
Also, the recovered character clock from the receive PLL is
passed to the reclocker output PLL which generates the bit
clock that is used to clock the retimed data into the output
register. This data stream is then transmitted through the
differential serial outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50
Ω
transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
reclocker serial drivers for a channel are in this disabled state,
the associated internal reclocker logic is also powered down.
The deserialization logic and parallel outputs will remain
enabled. A device reset (RESET sampled LOW) disables all
output drivers.
Note
. When the disabled reclocker function (i.e., both outputs
disabled) is re-enabled, the data on the reclocker serial
outputs may not meet all timing specifications for up to 250
μ
s.
Output Bus
The receive channel presents a 10-bit data signal (and a BIST
status signal when RXBISTx[1:0] = 10).
Receive BIST Operation
Each receiver channel contains an internal pattern checker
that can be used to validate both device and link operation.
These pattern checkers are enabled by the associated
RXBISTx[1:0] latch via the device configuration interface.
When enabled, a register in the associated receive channel
becomes a signature pattern generator and checker by
logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Trans-
mitter(s). When synchronized with the received data stream,
the associated Receiver checks each character from the
deserializer with each character generated by the LFSR and
indicates compare errors and BIST status at the RXDx[1:0]
and BISTSTx bits of the Output Register.
The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates
010b or 100b for one character period per BIST loop to
indicate loop completion. This status can be used to check test
pattern progress.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state
machine aborts the compare operations and resets the LFSR
to look for the start of the BIST sequence again.
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on both channels.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the {BISTSTx,
RXDx[0], RXDx[1]} bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2 on page 20
and
Table 6 on page 19
. When the receive
PLL detects an out-of-lock condition, the BIST state is forced
to the Start-of-BIST state, regardless of the present state of the
BIST state machine. If the number of detected errors ever
exceeds the number of valid matches by greater than 16, the
state machine is forced to the WAIT_FOR_BIST state where
it monitors the receive path for the first character of the next
BIST sequence.
Power Control
The CYV15G0204TRB supports user control of the powered
up or down state of each transmit and receive channel. The
receive channels are controlled by the RXPLLPDx latch via the
device configuration interface. When RXPLLPDx = 0, the
associated PLL and analog circuitry of the channel is disabled.
The transmit channels are controlled by the TOE1x and the
TOE2x latches via the device configuration interface. The
reclocker function is controlled by the ROE1x and the ROE2x
latches via the device configuration interface. When a driver is
disabled via the configuration interface, it is internally powered
down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic
for that channel is also powered down. When the reclocker
serial drivers are disabled, the reclocker function will be
disabled, but the deserialization logic and parallel outputs will
remain enabled.
Device Reset State
When the CYV15G0204TRB is reset by assertion of RESET,
all state machines, counters, and configuration latches in the
device are initialized to a reset state. Additionally, the JTAG
controller must also be reset for valid operation (even if JTAG
testing is not performed). See
“JTAG Support” on page 19
for
JTAG state machine initialization. See
Table 4 on page 16
for
the initialize values of the configuration latches.
Following a device reset, it is necessary to enable the receive
channels used for normal operation. This can be done by
sequencing the appropriate values on the device configuration
interface.
[5]
Device Configuration and Control Interface
The CYV15G0204TRB is highly configurable via the configu-
ration interface. The configuration interface allows each
channel to be configured independently.
Table 4 on page 16
lists the configuration latches within the device including the
initialization value of the latches upon the assertion of RESET.
Table 5 on page 18
shows how the latches are mapped in the
device. Each row in the
Table 5
maps to a 7-bit latch bank.
[+] Feedback
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