- 您現(xiàn)在的位置：買賣IC網 > PDF目錄380227 > CYV15G0204TRB (Cypress Semiconductor Corp.) Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer PDF資料下載
參數(shù)資料
| 型號： | CYV15G0204TRB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| 中文描述： | 獨立時鐘的HOTLink二⑩雙串行解串器和雙時鐘重計 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 389K |
| 代理商： | CYV15G0204TRB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 16 of 31
There are 12 such write-only latch banks. When WREN = 0,
the logic value in the DATA[7:0] is latched to the latch bank
specified by the values in ADDR[3:0]. The second column of
Table 5
specifies the channels associated with the corre-
sponding latch bank. For example, the first three latch banks
(0,1 and 2) consist of configuration bits for channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The
third row of latches for each channel (address numbers 2, 5,
8, and 11) are the dynamic control latches that are associated
with enabling dynamic functions within the device.
Static Latch Values
There are some latches in the table that have a static value
(i.e., 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
Table 4. Device Configuration and Control Latch Descriptions
Name
TXCKSELA
TXCKSELB
Signal Description
Transmit Clock Select
. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register
TXDx[9:0] is clocked by REFCLKx
↑.
In this mode, the phase alignment buffer in the transmit path is bypassed.
When TXCKSELx = 0, the associated TXCLKx
↑
is used to clock in the input register TXDx[9:0].
Transmit PLL Clock Rate Select
. The initialization value of the TXRATEx latch = 0. TXRATEx is used to
select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx
output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input.
When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the
serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the
REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using
both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx = LOW, is an invalid state and
this combination is reserved.
Transmit Bist Disabled
. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0,
the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable
. The initialization value of the TOE2x latch = 0.
TOE2x selects if the TOUTx2± secondary differential output drivers are enabled or disabled. When TOE2x =
1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When TOE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset
(RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable
. The initialization value of the TOE1x latch = 0.
TOE1x selects if the TOUTx1± primary differential output drivers are enabled or disabled. When TOE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When TOE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset
(RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset
. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx
↑
to synchronize it to the internal clock
domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the
initialization of the Phase Alignment Buffer.
TXRATEA
TXRATEB
TXBISTA
TXBISTB
TOE2A
TOE2B
TOE1A
TOE1B
PABRSTA
PABRSTB
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CYV15G0204TRB-BGC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGXC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0401DXB | Quad HOTLink II Transceiver |
| CYV15G0401DXB-BGC | Quad HOTLink II Transceiver |
| CYV15G0401DXB-BGI | Quad HOTLink II Transceiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204TRB-BGC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204TRB-BGXC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
| CYV15G0401DXB-BGC | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0401DXB-BGI | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。