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參數(shù)資料
| 型號(hào)： | CYV15G0204TRB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 389K |
| 代理商： | CYV15G0204TRB-BGXC |
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CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 23 of 31
CYV15G0204TRB AC Electrical Characteristics
Parameter
CYV15G0204TRB Transmitter LVTTL Switching Characteristics
Over the Operating Range
f
TS
TXCLKx Clock Cycle Frequency
t
TXCLK
TXCLKx Period=1/f
TS
t
TXCLKH[16]
TXCLKx HIGH Time
t
TXCLKL[16]
TXCLKx LOW Time
t
TXCLKR [16, 17, 18, 19]
TXCLKx Rise Time
t
TXCLKF [16, 17, 18, 19]
TXCLKx Fall Time
t
TXDS
Transmit Data Set-up Time to
TXCLKx
↑
(TXCKSELx
=
0)
t
TXDH
Transmit Data Hold Time from TXCLKx
↑
(TXCKSELx
=
0)
f
TOS
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
t
TXCLKO
TXCLKOx Period=1/f
TOS
t
TXCLKOD
TXCLKO Duty Cycle centered at 60% HIGH time
CYV15G0204TRB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
t
RXCLKR [16]
RXCLKx± Rise Time
t
RXCLKF [16]
RXCLKx± Fall Time
t
RXDv–[20]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
t
RXDv+[20]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)
f
ROS
RECLKOx Clock Frequency
t
RECLKO
RECLKOx Period=1/f
ROS
t
RECLKOD
RECLKOx Duty Cycle centered at 60% HIGH time
CYV15G0204TRB REFCLKx Switching Characteristics
Over the Operating Range
f
REF
REFCLKx Clock Frequency
t
REFCLK
REFCLKx Period = 1/f
REF
t
REFH
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
t
REFL
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
t
REFD[22]
REFCLKx Duty Cycle
t
REFR [16, 17, 18, 19]
REFCLKx Rise Time (20%–80%)
t
REFF[16, 17, 18, 19]
REFCLKx Fall Time (20%–80%)
t
REFRX[23]
TRGCLKx Frequency Referenced to Received Clock Period
Notes
16.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
17.The ratio of rise time to falling time must not vary by greater than 2:1.
18.For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
19.All transmit AC timing parameters measured with 1-ns typical rise time and fall time.
20.Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
21.Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TRGRATEx = 1) or 1/(f
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t
.
22.cannot be as large as 30%–70%.
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLKx± duty cycle
23.TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within
±
1500 PPM (
±
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
Description
Min.
Max
Unit
19.5
6.66
2.2
2.2
0.2
0.2
2.2
1.0
19.5
6.66
–1.9
150
51.28
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
1.7
1.7
150
51.28
0
9.75
6.66
–1.0
0.3
0.3
150
102.56
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
5UI–2.0
[21]
5UI–1.3
[21]
5UI–1.8
[21]
5UI–2.6
[21]
19.5
6.66
-1.9
150
51.28
0
19.5
6.6
5.9
2.9
[16]
5.9
2.9
[16]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
%
70
2
2
–0.15
+0.15
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
| CYV15G0401DXB-BGC | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0401DXB-BGI | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0401DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0401DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
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