參數(shù)資料
型號: CYV15G0204TRB-BGXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256
文件頁數(shù): 22/31頁
文件大小: 389K
代理商: CYV15G0204TRB-BGXC
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 22 of 31
AC Test Loads and Waveforms
Differential CML Serial Outputs: TOUTA1
±
, TOUTA2
±
, TOUTB1
±
, TOUTB2
±,
ROUTC1
±
, ROUTC2
±
, ROUTD1
±
, ROUTD2
±
V
OHC
Output HIGH Voltage
(V
cc
Referenced)
150
Ω
differential load
V
OLC
Output LOW Voltage
(V
CC
Referenced)
150
Ω
differential load
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
150
Ω
differential load
Differential Serial Line Receiver Inputs: INC1
±
, INC2
±
, IND1
±
, IND2
±
V
DIFFs[9]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
V
IN
= V
IHE
Max.
I
ILE
Input LOW Current
V
IN
= V
ILE
Min.
VI
COM[11]
Common Mode input range
((V
CC
– 2.0V)+0.5)min,
(V
CC
– 0.5V) max.
Power Supply
I
CC [12, 13]
Max Power Supply Current
REFCLKx =
MAX
I
CC [12, 13]
Typical Power Supply Current
REFCLKx =
125 MHz
100
Ω
differential load
V
CC
– 0.5
V
CC
– 0.5
V
CC
– 1.4
V
CC
– 1.4
450
560
V
CC
– 0.2
V
CC
– 0.2
V
CC
– 0.7
V
CC
– 0.7
900
1000
V
V
V
V
100
Ω
differential load
100
Ω
differential load
mV
mV
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
– 2.0
1350
–700
+1.25
+3.1
Typ.
810
Max.
990
Commercial
mA
Commercial
770
950
mA
CYV15G0204TRB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Notes
11. The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
12.Maximum I
is measured with V
CC
= MAX, T
A
= 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
13.Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, with all channels enabled and one Serial Line Driver per transmit channel
sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
14.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
15.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
270 ps
270 ps
[15]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
Ω
R2 = 435
Ω
C
L
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
Ω
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[14]
[14]
[+] Feedback
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