參數(shù)資料
型號(hào)： CYV15G0204TRB-BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256
文件頁(yè)數(shù)： 19/31頁(yè)
文件大?。?/td> 389K
代理商： CYV15G0204TRB-BGXC
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 19 of 31
JTAG Support
The CYV15G0204TRB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs, the
REFCLKx± clock inputs, and the TRGCLKx± clock inputs. The
high-speed serial inputs and outputs are not part of the JTAG
test chain.
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine should also be
initialized to a reset state. This should be done in addition to
the device reset (using RESET). The JTAG state machine can
be initialized using TRST (asserting it LOW and de-asserting
it or leaving it asserted), or by asserting TMS HIGH for at least
5 consecutive TCLK cycles. This is necessary in order to
ensure that the JTAG controller does not enter any of the test
modes after device power-up. In this JTAG reset state, the rest
of the device will be in normal operation.
Note
. The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0204TRB is ‘0C811069’x
Table 6. Receive Character Status Bits
{BISTSTx, RXDx[0], RXDx[1]}
Description
Receive BIST Status
(Receive BIST = Enabled)
000, 001
010
011
100
101
BIST Data Compare
. Character compared correctly.
BIST Last Good
. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad
.
Last Character of BIST sequence detected invalid.
BIST Start
. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error
. While comparing characters, a mismatch was found in one or more of the
character bits.
BIST Wait
. The receiver is comparing characters. but has not yet found the start of BIST
character to enable the LFSR.
110
111
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYV15G0401DXB 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver
CYV15G0401DXB-BGC 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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CYV15G0401DXB-BGXC 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYV15G0401DXB-BGXI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver
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