參數(shù)資料
型號(hào)： CYV15G0204TRB-BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256
文件頁(yè)數(shù)： 10/31頁(yè)
文件大小： 389K
代理商： CYV15G0204TRB-BGXC
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 10 of 31
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable
. When LDTDEN is HIGH, the Signal Level
Detector, Range Controller, and Transition Density Detector are all enabled to
determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream.
If the Signal Level Detector, Range Controller, or Transition Density Detector are out
of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx± until
such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is one
transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range
Controller is used to determine if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. It is recommended to set LDTDEN = HIGH.
Use Local Clock
. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from TRGCLKx±.
Serial Rate Select
. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s transmit (channels A and B) or receive PLL (channels C and D).
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector
. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential Serial
Data Input, INx2±, is selected for the associated receive channel.
Link Fault Indication Output
. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the following
conditions is true:
Received serial data rate outside expected range
Analog amplitude below expected levels
Transition density lower than expected
Receive channel disabled
ULCx is LOW
Absence of TRGCLKx±.
ULCC
ULCD
LVTTL Input,
internal pull-up
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select
[4]
static control input
INSELC
INSELD
LVTTL Input,
asynchronous
LFIC
LFID
LVTTL Output,
asynchronous
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Write Enable
. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
[5]
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
[5]
Table 4 on page
16
lists the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET.
Table 5 on page 18
shows how the latches are
mapped in the device.
Notes
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5. See
Device Configuration and Control Interface
for detailed information on the operation of the Configuration Interface.
Pin Definitions
(continued)
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
Name
I/O Characteristics
Signal Description
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
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CYV15G0401DXB-BGI 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYV15G0401DXB-BGXC 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYV15G0401DXB-BGXI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver
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