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參數(shù)資料
| 型號(hào)： | CYU01M16SCG |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Pseudo Static RAM |
| 中文描述： | 16兆位（1米× 16）偽靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | CYU01M16SCG |
PRELIMINARY
CYU01M16SCG
MoBL3
Document #: 001-09739 Rev. **
Page 5 of 11
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
CD
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Chip Deselect Time CE
1
= HIGH or
CE
2
=LOW, BLE/BHE High Pulse Time
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
[10, 11, 12]
WE HIGH to Low-Z
[10, 11, 12]
70
60
60
15
40000
ns
ns
ns
ns
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Note:
15.The internal Write time of the memory is defined by the overlap of WE, CE
= V
or CE
=
V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
0
0
50
60
25
0
ns
ns
ns
ns
ns
ns
ns
ns
25
10
Switching Characteristics
Over the Operating Range
[9, 10, 11, 14, 15]
(continued)
Parameter
Description
70 ns
Unit
Min.
Max.
[+] Feedback
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| CYU01M16SFE | 16-Mbit (1M x 16) Pseudo Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYU01M16SCG-70BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYU01M16SFCU | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYU01M16SFCU-70BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYU01M16SFE | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYU01M16SFEU-70BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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