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參數(shù)資料
| 型號： | CYU01M16SCG |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (1M x 16) Pseudo Static RAM |
| 中文描述： | 16兆位（1米× 16）偽靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 502K |
| 代理商： | CYU01M16SCG |
PRELIMINARY
CYU01M16SCG
MoBL3
Document #: 001-09739 Rev. **
Page 4 of 11
AC Test Loads and Waveforms
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
TH
Equivalent to:
THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Parameters
R1
R2
R
TH
V
TH
3.0V (V
CC
)
26000
26000
13000
1.50
Unit
V
Switching Characteristics
Over the Operating Range
[9, 10, 11, 14, 15]
Parameter
Read Cycle
t
RC[13]
t
CD
Description
70 ns
Unit
Min.
Max.
Read Cycle Time
Chip Deselect Time CE
1
= HIGH or
CE
2
=LOW, BLE/BHE High Pulse Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[10, 11, 12]
OE HIGH to High Z
[10, 11, 12]
CE LOW to Low Z
[10, 11, 12]
CE HIGH to High Z
[10, 11, 12]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[10, 11, 12]
BLE/BHE HIGH to High Z
[10, 11, 12]
70
15
40000
ns
ns
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
CC(typ.)
/2, input pulse levels
of 0V to V
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
10.At any given temperature and voltage conditions t
is less than t
, t
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
12.High-Z and Low-Z parameters are characterized and are not 100% tested.
13.If invalid address signals shorter than min.tRC are continuously repeated for 40
μ
s, the device needs a normal read timing (t
RC
) or needs to enter standby state
at least once in every 40
μ
s.
14.In order to achieve 70-ns performance, the read access must be Chip Enable (CE
1
or CE
2
) controlled. That is, the addresses must be stable prior to Chip Enable
going active.
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
70
35
5
25
10
25
70
5
25
ns
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