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參數(shù)資料
| 型號： | CYP15G0402DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | 四HOTLinkII的SERDES |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 27 of 27
Document Title: CYP15G0402DX Quad HOTLinkII
SERDES
Document Number: 38-02023
Issue
Date
**
108363
07/11/01
*A
108915
07/31/01
*B
112986
03/01/02
REV.
ECN NO.
Orig. of
Change
TME
AMV
TPS
Description of Change
New Data Sheet
Changed name of part from PHY to SERDES
Changed common mode input specs to match 401D part pp. 17, 18
Added engineering changes to half-rate timing. p. 22
Updated the spec as per meeting with engineering pp. 20
–
23
Changed the Refclock input to VLTTL both inputs p. 9
Addition of TXCLKO N and the TXCLKO P specs p. 22
Changed the TXCLKO clock output to reflect the new timing p. 22
Changed the Half Clock drawing so that the valid time was at clock edges
Changed the input power input p. 21, p. 22 max. power
Changed the spec for serial output levels at the different terminations.
Changed the common mode input range of serial input
Increased the serial input current under the conditions of V
CC
and min.
Added to the duty cycle of transmit and receiver clock signals
Changed rise time of the serial inputs and receiver
Changed half-rate timing drawing from not valid at clock edges to valid at
clock edges
Max. voltage reduced from 4.2 to 3.8
Matched the common specs with the family of parts pp. 21
–
24
Changed max output current to 35 Ma p. 20
Corrected period timing of min. clock from 100 ns to 50 ns p. 19
Added
“
Preliminary
”
Added pin RXCKSEL to the pin layout p. 6, 7 to pin layout and pin descriptions
Change min. clock frequency
Change the front pages
Remove decoder command from p. 16, as it is no longer used.
相關PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
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