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參數(shù)資料
| 型號： | CYP15G0402DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | 四HOTLinkII的SERDES |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 19 of 27
CYP15G0402DX Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
t
B
t
RISE
Description
Condition
Min.
5000
50
100
200
50
100
200
Max.
660
270
500
1000
270
500
1000
0.1
0.2
192
TBD
Unit
ps
ps
ps
ps
ps
ps
ps
UI
UI
ps
ns
Bit Time
CML Output Rise Time 20
80% (CML Test Load)
[13]
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
t
FALL
CML Output Fall Time 80
20% (CML Test Load)
[13]
t
DJ
t
TJ
Deterministic Jitter (peak-peak)
[14, 17
Total Jitter (
σ
)
[15, 17]
0.2-1.0Gbps
1.0-1.5Gbps
t
TXLOCK
Transmit PLL lock to REFCLK
TBD
Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
Parameter
t
RXLOCK
Description
Min.
Max.
10
2500
TBD
Unit
ms
UI
ns
ps
UI
Receive PLL Lock to Input Data Stream
Receive PLL Lock to Input Data Stream
Receive PLL Unlock Rate
Static Alignment
[16]
Error-free Window
[14, 17, 18]
t
RXUNLOCK
t
SA
t
EFW
Notes:
13. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within
±
200- ppm (
±
0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a
±
100-ppm crystal.
14. While sending continuous K28.5s, outputs loaded to a balanced 100
load, over the operating range.
15. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
operating range.
16. Static alignments is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a character error occurs.
17. Receiver UI is calculated as 1/Fref*10 when RXRATE = LOW if no data is being received of the remote transmitter. If data is being received it is equal to
1/transmit serial bit rate.
18. Error Free Window is a measure of the time window between the bit centers where a transition may occur without causing a sampling error. It is measured
over the operational range.
TBD
0.75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
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