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參數(shù)資料
| 型號： | CYP15G0402DX-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX-BGC |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 8 of 27
Receive Path Data Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
COMDETA
COMDETB
COMDETC
COMDETD
RXOPA
RXOPB
RXOPC
RXOPD
RXRATE
LVTTL Output,
synchronous
Receive Data Output
. These outputs change following the rising edge of the associated
RXCLKx
±
clock.
LVTTL Output,
synchronous
Frame Character Detected
. The character in the output register matches that of the
selected framing character.
Three-state, LVTTL
Output
Receive Path Odd Parity
. When PARCTL isn
’
t low parity generation is enabled, the
parity output at these pins is valid for the data on the associated RXDx bus bits. When
PARCTL=LOW parity generation is disabled, these output drivers are High-Z.
LVTTL Input
Static Control Input
Receive Clock Rate Select
. When LOW, the RXCLKx
±
recovered clock outputs are
complementary clocks operating at the recovered character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of
RXCLKx
–
. When HIGH, the RXCLKx
±
recovered clock outputs are complementary
clocks operating at half the character rate. Data for the associated receive channels
should be latched alternately on the rising edge of RXCLKx+ and RXCLKx
–
. When
operating with REFCLK clocking of the received parallel data outputs both RXCKSEL
and RXRATE must be LOW.
Reference Clock
. This clock input is used as the timing reference for the transmit and
receive PLLs. This input clock may also be selected to clock the transmit and receive
parallel interfaces. For an LVCMOS or LVTTL input clock connect clock source to
REFCLK to the input pin and float the other REFCLK
–
. For an LVPECL input level input
clock has to be a differential clock, using both inputs. For an LVPECL differential clock,
both inputs must have a phase difference of 180 degrees. When TXCKSEL is LOW, a
character-rate derivative of REFCLK is used as the clock for the parallel transmit data
input interface.
Serial Rate Select
. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 200
–
400 MBaud, MID = 400
–
800 MBaud, HIGH =
800
–
1500 MBaud.
REFCLK
±
Differential LVPECL
or single-ended
LVCMOS input clock
SPDSEL
3-Level Select
[1]
,
Static Control Input
Analog I/O and Control
OUTA
±
OUTB
±
OUTC
±
OUTD
±
INA
±
INB
±
INC
±
IND
±
SDASEL
CML Differential
Output
Differential Serial Data Outputs
. These CML outputs are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules.
LVPECL Differential
Input
Differential Serial Data Inputs
. These inputs accept the serial data stream for deseri-
alization and decoding. The INx
±
serial stream is fed to the receiver to extract the data
and clock content when LPENx is LOW.
3-Level Select
[1]
,
static configuration
input
LVTTL Input,
asynchronous,
internal pull-down
Signal Detect Amplitude Level Select
. Allows selection of one of three predefined
amplitude trip points for a valid signal indication, as listed in
Table 4
.
LPENA
LPENB
LPENC
LPEND
Loop-Back-Enable
. When HIGH, the transmit serial data from the associated channel
is internally routed to its respective receiver clock and data recovery (CDR) circuit. The
serial output for the channel where LPENx is active is forced to differential logic-1, and
serial data inputs for that channel are ignored.
Pin Descriptions
Quad HOTLink II SERDES
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DX-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
| CYP15G0402DX-EVAL | 功能描述:界面開發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYP15G0403DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
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