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參數(shù)資料
| 型號(hào)： | CYP15G0402DX-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX-BGC |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 12 of 27
Serial Output Drivers
The serial interface Output Drivers make use of differential
Current Mode Logic to provide a source-matched driver for the
transmission lines. These drivers accept data from the
Transmit Shifters. These outputs have signal swings equiv-
alent to that of standard PECL drivers, and are capable of
driving AC-coupled optical modules or transmission lines.
When configured for internal local loopback test, LPEN =
HIGH, the output drivers for all enabled ports are configured
to drive a static differential logic-1.
Each output can be enabled or disabled separately through the
BOE[7:0] inputs, as controlled by the OELE latch-enable
signal. When OELE is HIGH, the signals present on the
BOE[7:0] inputs are passed through the Serial Output Enable
latch to control the serial output drivers. The BOE[7:0] input
associated with a specific OUTx
±
driver is listed in
Table 2
.
When OELE is HIGH and BOE[x] is HIGH, the associated
serial driver is enabled. When OELE is HIGH and BOE[x] is
LOW, the associated driver is disabled and in a power down
mode. If both outputs for a channel are disabled, the
associated internal logic for that channel is also configured for
low power operation. When OELE returns LOW, the values
present on the BOE[7:0] inputs are latched in the Output
Enable Latch, and remain there until OELE returns HIGH to
opened the latch again.
Note
. When a disabled transmit
channel is re-enabled, the data on the serial outputs may not
meet all timing specifications for up to 10 ms.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiplies that clock by 10 or 20 to generate a bit-rate clock for
use by the transmit Shifter.
The clock multiplier PLL can accept a REFCLK input between
10 MHz and 150 MHz, however, this clock range of the PLL is
controlled by the TXRATE and SPDSEL input signals of the
CYP15G0402DX.
SPDSEL is a 3-level select
[1]
(ternary) input that selects one
of three operating ranges for the serial data outputs and
inputs. The operating serial signalling rate and allowable
range of REFCLK frequencies is listed in
Table 3
.
The REFCLK
±
input is a differential input with each input inter-
nally biased to 1.5V. If the REFCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when the clock signal passes through the internal
biased point.
When both the REFCLK+ and REFCLK
inputs are
connected, the clock source must be a differential clock. This
can be either a LVPECL clock, or a differential LVTTL or
LVCMOS clock.
Table 2. Output Enable, BIST, and Receive Channel Enable Signal Map
BOE Input
Output Controlled (OELE)
BIST Channel Enable
(BISTLE)
Receive PLL Channel
Enable (RXLE)
BOE[7]
X
Transmit D
X
BOE[6]
OUTD
±
Receive D
Receive D
BOE[5]
X
Transmit C
X
BOE[4]
OUTC
±
Receive C
Receive C
BOE[3]
X
Transmit B
X
BOE[2]
OUTB
±
Receive B
Receive B
BOE[1]
X
Transmit A
X
BOE[0]
OUTA
±
Receive A
Receive A
Table 3. Operating Speed Settings
SPDSEL
TXRATE
REFCLK
Frequency
(MHz)
Signaling
Rate
(MBaud)
LOW
1
20
200
–
400
0
20
–
40
MID (Open)
1
20
–
40
400
–
800
0
40
–
80
HIGH
1
40
–
75
800
–
1500
0
80
–
150
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DX-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
| CYP15G0402DX-EVAL | 功能描述:界面開發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYP15G0403DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
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