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參數(shù)資料
| 型號： | CYP15G0401DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大小： | 1115K |
| 代理商： | CYP15G0401DXB-BGI |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 8 of 48
TXRST
LVTTL Input, asyn-
chronous,
internal pull-up,
sampled by
TXCLKA
↑
or
REFCLK
↑
[1]
Transmit Clock Phase Reset, active LOW. When LOW, the transmit Phase-Align Buffers
are allowed to adjust their data-transfer timing (relative to the selected input clock) to
allow clean transfer of data from the input register to the encoder or transmit shift reg-
ister. When TXRST is deasserted (HIGH), the internal phase relationship between the
associated TXCLKx and the internal character-rate clock is fixed and the device oper-
ates normally.
When configured for half-rate REFCLK sampling of the transmit character stream (TX-
CKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear phase
align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs with
excessive cycle-to-cycle jitter.
During this alignment period, one or more characters may be added to or lost from all
the associated transmit paths as the transmit Phase-Align Buffers are adjusted.
TXRST must be sampled LOW by a minimum of two consecutive rising edges of TX-
CLKA (or one REFCLK
↑
) to ensure the reset operation is initiated correctly on all chan-
nels.
This input is not interpreted when both TXCKSEL and TXRATE are LOW.
Special Character Select. Used in some transmit modes along with TXCTx[1:0] to en-
code special characters or to initiate a Word Sync Sequence. When the transmit paths
are configured for independent inputs clocks (TXCKSEL = MID), SCSEL is captured
relative to TXCLKA
↑
.
SCSEL
LVTTL Input,
synchronous,
internal pull-down,
sampled by
TXCLKA
↑
or REFCLK
↑
[1]
Transmit Path Clock and Clock Control
TXCKSEL
3-Level Select
[2]
Static Control Input
Transmit Clock Select. Selects the transmit clock source, used to write data into the
transmit input register, for the transmit channel(s).
When LOW, all four input registers are clocked by REFCLK
↑
[1]
.
When MID, TXCLKx
↑
is used as the input register clock for TXDx[7:0] and TXCTx[1:0].
When HIGH, TXCLKA
↑
is used to clock data into the input register of each channel.
Transmit Clock Output. This true and complement output clock is synthesized by the
transmit PLL and operates synchronous to the internal transmit character clock. It op-
erates at either the same frequency as REFCLK, or at twice the frequency of REFCLK
(as selected by TXRATE). TXCLKO
±
is always equal to the transmit VCO bit-clock
frequency
÷
10. This output clock has no direct phase relationship to REFCLK or any
recovered character clock.
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit
PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See
Table 11
for a list
of operating serial rates.
When REFCLK is selected for clocking of the receive parallel interfaces (RXCKSEL =
LOW), the TXRATE input also determines if the clock on the RXCLKA
±
and RXCLKC
±
outputs is a full or half-rate clock. When TXRATE = HIGH, these output clocks are half-
rate clocks and follow the frequency and duty cycle of the REFCLK input. When TXRATE
= LOW, these output clocks are full-rate clocks and follow the frequency and duty cycle
of the REFCLK input.
Transmit path input clocks. These clocks must be frequency-coherent to TXCLKO
±
, but
may be offset in phase. The internal operating phase of each input clock (relative to
REFLCK) is adjusted when TXRST = LOW and locked when TXRST = HIGH.
TXCLKO
±
LVTTL Output
TXRATE
LVTTL Input,
Static Control input,
internal pull-down
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input,
internal
pull-down
Note:
2.
3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). When
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXB-BGXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGXCKG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXBBGXI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXB-BGXI | 功能描述:電信線路管理 IC Quad HOTLink II XCVR Ch 1.5Gbps Backplane RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DX-BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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