參數(shù)資料
型號(hào)： CYP15G0401DXB-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： BGA-256
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 1115K
代理商： CYP15G0401DXB-BGI
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 11 of 48
Device Control Signals
PARCTL
3-Level Select
[2]
Static Control Input
Parity Check/Generate Control. Used to control the different parity check and generate
functions.
When LOW, parity checking is disabled, and the RXOPx outputs are all disabled
(High-Z).
When MID, and the encoder/decoder are enabled (TXMODE[1]
≠
L, RXMODE[1]
≠
L),
TXDx[7:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity
is generated for the RXDx[7:0] outputs and presented on RXOPx. When the encoder
and decoder are disabled (TXMODE[1]
=
L, RXMODE[1]
=
L), theTXDx[7:0] and
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity
is generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on RXOPx.
When HIGH, the and the encoder/decoder are enabled (TXMODE[1]
≠
L,
RXMODE[1]
≠
L), the TXDx[7:0] and TXCTx[1:0] inputs are checked (along with
TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[7:0] and
RXSTx[2:0] outputs and presented on RXOPx. When the encoder is and decoder are
disabled (TXMODE[1]
=
L, RXMODE[1]
=
L), theTXDx[7:0] and TXCTx[1:0] inputs are
checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the
RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx.
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 200
–
400 MBd, MID = 400
–
800 MBd, HIGH = 800
–
1500 MBd.
SPDSEL
3-Level Select
[2]
,
static configuration
input
Differential LVPECL
or single-ended
LVTTL input clock
REFCLK
±
Reference Clock. This clock input is used as the timing reference for the transmit and
receive PLLs. This input clock may also be selected to clock the transmit and receive
parallel interfaces. For an LVCMOS or LVTTL input clock, connect REFCLK+ to the
reference clock and leave REFCLK
–
open. For an LVPECL differential clock, both inputs
must be connected.
When TXCKSEL = LOW, REFCLK is used as the clock for the parallel transmit data
(input) interface.
When RXCKSEL = LOW, REFCLK is used as the clock for the parallel receive data
(output) interface.
Analog I/O and Control
OUTA1
±
OUTB1
±
OUTC1
±
OUTD1
±
OUTA2
±
OUTB2
±
OUTC2
±
OUTD2
±
INA1
±
INB1
±
INC1
±
IND1
±
INA2
±
INB2
±
INC2
±
IND2
±
INSELA
INSELB
INSELC
INSELD
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V
referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules. These outputs must be AC-coupled for PECL-compatible connec-
tions.
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compati-
ble connections.
Primary Differential Serial Data Inputs. These inputs accept the serial data stream for
deserialization and decoding. The INx1
±
serial streams are passed to the receiver Clock
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.
CML Differential
Output
LVPECL Differential
Input
LVPECL Differential
Input
Secondary Differential Serial Data Inputs. These inputs accept the serial data stream
for deserialization and decoding. The INx2
±
serial streams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when
INSELx = LOW.
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1
±
input is selected.
When LOW, the INx2
±
input is selected.
LVTTL Input,
asynchronous
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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CYP15G0401DXB-BGXC 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0401DXB-BGXCKG 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CYP15G0401DXBBGXI 制造商:Cypress Semiconductor 功能描述:
CYP15G0401DXB-BGXI 功能描述:電信線路管理 IC Quad HOTLink II XCVR Ch 1.5Gbps Backplane RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0401DX-BGC 制造商:Rochester Electronics LLC 功能描述:- Bulk
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