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參數(shù)資料
| 型號： | CYP15G0401DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 1115K |
| 代理商： | CYP15G0401DXB-BGI |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 12 of 48
SDASEL
3-Level Select
[2]
,
static configuration
input
LVTTL Input,
asynchronous,
internal pull-down
Signal Detect Amplitude Level Select. Allows selection of one of three predefined am-
plitude trip points for a valid signal indication, as listed in
Table 12
.
LPEN
All-Port Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial
data from each channel is internally routed to the associated receiver Clock and Data
Recovery (CDR) circuit. All serial drivers are forced to differential logic
“
1
”
. All serial data
inputs are ignored.
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the sig-
nals on the BOE[7:0] inputs directly control the OUTxy
±
differential drivers. When the
BOE[x] input is HIGH, the associated OUTxy
±
differential driver is enabled. When the
BOE[x] input is LOW, the associated OUTxy
±
differential driver is powered down. When
OELE returns LOW, the last values present on BOE[7:0] are captured in the internal
Output Enable latch. The specific mapping of BOE[7:0] signals to transmit output en-
ables is listed in
Table 10
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to enable all outputs.
Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables.
When BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associ-
ated transmit or receive channel is configured for normal data transmission or reception.
When BISTLE returns LOW, the last values present on BOE[7:0] are captured in the
internal BIST Enable latch. The specific mapping of BOE[7:0] signals to transmit and
receive BIST enables is listed in
Table 10
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to disable BIST on all transmit and receive channels.
Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the
signals on the BOE[7:0] inputs directly control the power enables for the receive PLLs
and analog logic. When the BOE[7:0] input is HIGH, the associated receive channel A
through receive channel D PLL and analog logic are active. When the BOE[7:0] input is
LOW, the associated receive channel A through receive channel D PLL and analog logic
are placed in a non-functional power saving mode. When RXLE returns LOW, the last
values present on BOE[7:0] are captured in the internal RX PLL Enable latch. The
specific mapping of BOE[7:0] signals to the associated receive channel enables is listed
in
Table 10
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to enable all receive channels.
BIST, Serial Output, and Receive Channel Enables.
These inputs are passed to and through the output enable latch when OELE is HIGH,
and captured in this latch when OELE returns LOW.
These inputs are passed to and through the BIST enable latch when BISTLE is HIGH,
and captured in this latch when BISTLE returns LOW.
These inputs are passed to and through the Receive Channel enable latch when RXLE
is HIGH, and captured in this latch when RXLE returns LOW.
Link Fault Indication output. Active LOW. LFI is the logical OR of four internal conditions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled
OELE
LVTTL Input,
asynchronous,
internal pull-up
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
RXLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[7:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LFIC
LFID
LVTTL Output,
synchronous to the
selected RXCLKx
↑
output or
REFCLK
↑
[1]
input,
asynchronous to
receive channel
enable/disable
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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PDF描述 |
|---|---|
| CYP15G0401DXA-BGC | Quad HOTLink II Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXB-BGXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGXCKG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXBBGXI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXB-BGXI | 功能描述:電信線路管理 IC Quad HOTLink II XCVR Ch 1.5Gbps Backplane RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DX-BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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