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參數資料
| 型號： | CYP15G0401DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數： | 23/48頁 |
| 文件大小： | 1115K |
| 代理商： | CYP15G0401DXB-BGI |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 23 of 48
When RFMODE = LOW, the low-latency framer is selected.
This framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode the framer starts its alignment process on the first
detection of the selected framing character. To reduce the im-
pact on external circuits that make use of a recovered clock,
the clock period is not stretched by more than two bit-periods
in any one clock cycle. When operated in with a character-rate
output clock (RXRATE = LOW), the output of properly framed
characters may be delayed by up to nine character-clock
cycles from the detection of the selected framing character.
When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters
may be delayed by up to 14 character-clock cycles from the
detection of the selected framing character.
When RFMODE is MID (open) the Cypress-mode multi-byte
framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to in-
correct framing due to aliased SYNC characters in the data
stream. In this mode, the framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock will not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode the character boundaries are only adjust-
ed if the selected framing character is detected at least twice
within a span of 50 bits, with both instances on identical 10-bit
character boundaries.
When RFMODE = HIGH, the alternate-mode multi-byte framer
is enabled. Like the Cypress-mode multi-byte framer, multiple
framing characters must be detected before the character
boundary is adjusted. In this mode, the data stream must con-
tain a minimum of four of the selected framing characters, re-
ceived as consecutive characters, on identical 10-bit bound-
aries, before character framing is adjusted.
NOTE:
Except for the K29.7 character, the 8B/10B running
disparity rules prohibit the presence of multiple COMMA+
characters as consecutive characters. Because of this, the
combination of FRAMCHAR LOW and RFMODE = HIGH is
not recommended. While framing can still take place while
following all 8B/10B coding rules, this configuration pre-
vents framing to the K28.5 character.
NOTE:
The receive Elasticity Buffers require detection of
four of the selected framing character to enable buffer align-
ment and centering. Because these characters must occur
as consecutive characters, the combination of FRAMCHAR
LOW and RFMODE = HIGH is not recommended for re-
ceive modes that use the Elasticity Buffers.
Framing for all channels is enabled when RFEN = HIGH. If
RFEN = LOW, the framer for each channel is disabled. When
the framers are disabled, no changes are made to the recov-
ered character boundaries on any channel, regardless of the
presence of framing characters in the data stream.
10B/8B Decoder Block
The decoder logic block performs three primary functions:
decoding the received transmission characters back into
Data and Special Character codes,
comparing generated BIST patterns with received charac-
ters to permit at-speed link and device testing,
and generation of ODD parity on the decoded characters.
10B/8B Decoder
The framed parallel output of each deserializer shifter is
passed to the 10B/8B Decoder where, if the Decoder is en-
abled (DECMODE
≠
LOW), it is transformed from a 10-bit
transmission character back to the original Data and Special
Character codes. This block uses the 10B/8B decoder pat-
terns in
Table 24
and
Table 25
of this data sheet. Valid data
characters are indicated by a 000b bit-combination on the as-
sociated RXSTx[2:0] status bits, and Special Character codes
are indicated by a 001b bit-combination on these same status
outputs. Framing characters, Invalid patterns, disparity errors, and
synchronization status are presented as alternate combinations of
these status bits.
The 10B/8B decoder operates in two normal modes, and can
also be bypassed. The operating mode for the decoder is con-
trolled by the DECMODE input.
When DECMODE = LOW, the decoder is bypassed and raw
10-bit characters are passed to the output register. In this
mode, channel bonding is not possible, the receive Elasticity
Buffers are bypassed, and RXCKSEL must be MID. This clock
mode generates separate RXCLKx
±
outputs for each receive
channel.
When DECMODE is MID (or open), the 10-bit transmission
characters are decoded using
Tables 24
and
25
. Received
Special Code characters are decoded using the Cypress col-
umn of
Table 25
.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using
Table 24
and
Table 25
. Received Special
Code characters are decoded using the Alternate column of
Table 25
.
In all settings where the decoder is enabled, the receive paths
may be operated as separate channels or bonded to form var-
ious multi-channel buses.
Receive BIST Operation
The receiver interfaces contain internal pattern generators that
can be used to validate both device and link operation. These
generators are enabled by the associated BOE[x] signals list-
ed in
Table 10
(when the BISTLE latch enable input is HIGH).
When enabled, a register in the associated receive channel
becomes a signature pattern generator and checker by logi-
cally converting to a Linear Feedback Shift Register (LFSR).
This LFSR generates a 511-character sequence that includes
all Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet pseudo-ran-
dom sequence that can be matched to an identical LFSR in
the attached Transmitter(s). When synchronized with the re-
ceived data stream, the associated receiver checks each char-
acter in the Decoder with each character generated by the
LFSR and indicates compare errors and BIST status at the
RXSTx[2:0] bits of the output register.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator/checker in the associated
receive channel (or the BIST generator in the associated trans-
mit channel). When BISTLE returns LOW, the values of all
BOE[x] signals are captured in the BIST Enable Latch. These
values remain in the BIST Enable Latch until BISTLE is re-
turned high to open the latch again. All captured signals in the
BIST Enable Latch are set HIGH (i.e., BIST is disabled) follow-
ing a device reset (TRSTZ is sampled LOW).
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相關代理商/技術參數 |
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|---|---|
| CYP15G0401DXB-BGXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGXCKG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXBBGXI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0401DXB-BGXI | 功能描述:電信線路管理 IC Quad HOTLink II XCVR Ch 1.5Gbps Backplane RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DX-BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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