- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYNSE70064A-50BGC (CYPRESS SEMICONDUCTOR CORP) Search Engine PDF資料下載
參數(shù)資料
| 型號： | CYNSE70064A-50BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 21/127頁 |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A-50BGC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁
CYNSE70064A
Document #: 38-02041 Rev. *E
Page 21 of 127
Cycle 1
: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
on the DQ bus, as shown in
Table 10-6
. The host ASIC selects the CYNSE70064A where ID[4:0] matches the DQ[25:21] lines.
If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set.
Cycle 2
: The host ASIC floats DQ[67:0] to the three-state condition.
Cycle 3
: The host ASIC keeps DQ[67:0] in the three-state condition.
Cycle 4
: The selected device starts to drive the DQ[67:0] bus and drives ACK and EOT from Z to LOW.
Cycle 5
: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal HIGH.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG
are complete. On the last transfer, the CYNSE70064A drives the EOT signal HIGH.
Cycle (4 + 2n)
: The selected device drives the DQ[67:0] to the three-state condition, and drives the ACK and EOT signals LOW.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to the three-state condition. The burst Read instruction
is complete, and a new operation can begin.
Table 10-6
describes the Read address format for data and mask arrays for burst
Read operations.
Table 10-6. Read Address Format for Data and Mask Arrays
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:15]
Reserved
ID
00: Data Array
Reserved
10.4
The Write can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst
Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask array locations.
A single-location Write is a 3-cycle operation, as shown in
Figure 10-3
. The burst Write adds one extra cycle for each successive
location Write.
cycle 1
cycle 0
Write Command
The following is the Write operation sequence, and
Table 10-7
shows the Write address format for the data array, the mask array,
or single-Write SRAM.
Table 10-8
shows the Write address format for the internal registers.
Cycle 1A:
The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied
on the DQ bus. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply the SADR[21:20] on CMD[8:7].
Cycle 1B:
The host ASIC continues to apply the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the
devices when DQ[25:21] = 11111.
Cycle 2:
The host ASIC drives the DQ[67:0] with the data to be written to the data array, mask array, or register location of
the selected device.
Cycle 3:
Idle cycle.
At the termination of cycle 3, another operation can begin.
Note
. The latency of the SRAM Write will be different than the one described above (see Subsection 12.2, “SRAM PIO Access”
on page 101).
DQ[14:0]
Do not care
. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
Do not care
. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
Reserved
ID
01: Mask Array
Reserved
cycle 2
cycle 3
Write
Address
Data
CMDV
CMD[1:0]
DQ
X
cycle 4
CMD[8:2]
B
PHS_L
A
CLK2X
Figure 10-3. Single Write Cycle Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYNSE70064A-66BGC | Search Engine |
| CYNSE70064A-83BGC | Search Engine |
| CYP15G0101DXA | Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBI | Single Channel HOTLink II Transceiver |
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70064A-66BG | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064A-66BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-83BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
| CYNSE70128-83BGC | 制造商:Cypress Semiconductor 功能描述:NETWORK SEARCH ENGINE 388BGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。