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| 型號(hào)： | CYNSE70064A-50BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272 |
| 文件頁數(shù)： | 101/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A-50BGC |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 101 of 127
12.1
Table 12-1. SRAM Bus Address
Command
Search
Learn
PIO Read
PIO Write
Indirect Access
Generating an SRAM BUS Address
12.2
The remainder of Section 12.0 describes SRAM Read and SRAM Write operations.
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will be depend
on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configu-
ration register.
Note
. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the selected
device performing the access.
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend
on the TLSZ value parameter programmed in the device configuration register.
Note
. SRAM Write is a pipelined operation—new
instruction can begin right after the previous command has ended.
SRAM PIO Access
12.3
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend on
the TLSZ value parameter programmed in the device configuration register. The latency of the ACK from the Read instruction is
the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register.
The following explains the SRAM Read operation in a table with only one device that has the following parameters: TLSZ = 00,
HLAT = 000, LRAM = 1, and LDEV = 1.
Figure 12-1
shows the associated timing diagram. For the following description, the
selected device refers to the only device in the table because it is the only device to be accessed.
Cycle 1A
: The host ASIC applies the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address,
with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7].
Cycle 1B
: The host ASIC continues to apply the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
Cycle 2
: The host ASIC floats DQ[67:0] to a three-state condition.
Cycle 3
: The host ASIC keeps DQ[67:0] in a three-state condition.
Cycle 4
: The selected device starts to drive DQ[67:0] and drives ACK from High-Z to LOW.
Cycle 5
: The selected device drives the Read address on SADR[21:0]; it also drives ACK HIGH, CE_L LOW, and ALE_L LOW.
Cycle 6
: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and
ACK LOW.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
SRAM Read with a Table of One Device
SRAM Operation
Read
Write
Read
Write
Write/Read
21
C8
C8
C8
C8
C8
20
C7
C7
C7
C7
C7
[19:15]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
[14:0]
Index[14:0]
NFA[14:0]
ADR14:0]
ADR[14:0]
SSR[14:0]
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