參數(shù)資料
型號: CYNSE70064A-50BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Search Engine
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA272
封裝: 27 X 27 MM, 2.33 MM HEIGHT, PLASTIC, BGA-272
文件頁數(shù): 100/127頁
文件大小: 3275K
代理商: CYNSE70064A-50BGC
CYNSE70064A
Document #: 38-02041 Rev. *E
Page 100 of 127
12.0
SRAM Addressing
Table 12-1
describes the commands used to generate addresses on the SRAM address bus. The index [14:0] field contains the
address of a 68-bit entry that results in a hit in 68-bit-configured partition. It is the address of the 68-bit entry that lies at the 136-bit
page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively.
Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[14:0] contains the address
supplied on the DQ bus during PIO access to the CYNSE70064A. Command bits 8, and 7 {CMD[8:7]} are passed from the
command to the SRAM address bus. See Section 10.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the
device driving the SRAM bus (see Section 18.0, “Pinout Descriptions and Package Diagrams” on page 121, for more information).
FULO[0]
6
5
4
FULI
3
2
1
0
FULO[0]
6
5
4
FULI
3
2
1
0
FULO[1]
6
5
4
FULI
3
2
1
0
FULO[0]
6
5
4
FULI
3
2
1
0
FULO[0]
6
5
4
FULI
3
2
1
0
FULO[0]
6
5
4
3
2
1
0
FULI
6
5
4
3
2
1
0
FULI
6
5
4
3
2
FULI
1
0
FULO[0]
FULI
FULI
FULI
FULO[1]
FULO[1]
FULO[1]
DQ[67:0]
FULO[1] FULO[0]
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
V
DDQ
CYNSE70064A
CYNSE70064A
CYNSE70064A
CYNSE70064A
CYNSE70064A
CYNSE70064A
CYNSE70064A
FULO[0]
CYNSE70064A
Figure 11-3. Full Generation in a Cascaded Table
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