參數(shù)資料
型號(hào): CYM1836V33
廠商: Cypress Semiconductor Corp.
英文描述: 128K x 32 3.3V Static RAM Module(128K x 32 3.3V 靜態(tài)RAM模塊)
中文描述: 128K的× 32 3.3靜態(tài)存儲(chǔ)器模塊(128K的× 32 3.3靜態(tài)內(nèi)存模塊)
文件頁(yè)數(shù): 4/7頁(yè)
文件大?。?/td> 260K
代理商: CYM1836V33
CYM1836V33
PRELIMINARY
4
WRITE CYCLE
[7]
t
WC
Write Cycle
Time
CS LOW to Write
End
Address Set-Up
to Write End
Address Hold
from Write End
Address Set-Up
to Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to Low
Z
WE LOW to High
Z
[6]
15
20
25
30
35
45
ns
t
SCS
12
15
15
18
20
25
ns
t
AW
12
15
15
18
20
25
ns
t
HA
0
0
0
0
0
0
ns
t
SA
0
0
0
0
0
0
ns
t
PWE
t
SD
12
7
15
10
15
10
18
13
20
15
25
20
ns
ns
t
HD
0
0
0
0
0
0
ns
t
LZWE
3
3
3
3
3
3
ns
t
HZWE
0
7
0
8
0
10
0
15
0
15
0
18
ns
Shaded area contains advance information.
Switching Characteristics
Over the Operating Range
[4]
(continued)
Parameter
Description
1836V33–15
Min.
1836V33–20
Min.
1836V33–25
Min.
1836V33–30
Min.
1836V33–35
Min.
1836V33–45
Min.
Unit
Max.
Max.
Max.
Max.
Max.
Max.
Switching Waveforms
Notes:
7.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
WE is HIGH for read cycle.
Device is continuously selected, CS = V
and OE= V
.
10. Address valid prior to or coincident with CS transition LOW.
8.
9.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
1836V33–6
ADDRESS
DATA OUT
Read
Cycle No.1
[8, 9]
DATA VALID
t
RC
t
ACS
t
DOE
t
LZOE
t
LZCS
HIGH IMPEDANCE
t
HZOE
t
HZCS
HIGH
IMPEDANCE
DATA OUT
OE
CS
1836V33–7
Read
Cycle No. 2
[8, 10]
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