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參數(shù)資料
| 型號(hào)： | CYM1840 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 32 Static RAM Module(256K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 256K × 32靜態(tài)RAM模塊（256K × 32靜態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | CYM1840 |
256K x 32 Static RAM Module
CYM1840
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
October 1990 – Revised June 1993
408-943-2600
1CYM1840
Features
High-density 8-megabit SRAM module
High-speed CMOS SRAMs
—
Access time of 20 ns
Independent byte and word controls
Low active power
—
6.2W (max.)
SMD technology
TTL-compatible inputs and outputs
Low profile
—
Max. height of .350 in.
Small PCB footprint
—
1.8 sq. in.
Functional Description
The CYM1840 is a high-performance 8-megabit static RAM
module organized as 256K words by 32 bits. This module is
constructed from eight 256K x 4 SRAMs in SOJ packages
mounted on an epoxy laminate substrate with pins. Four chip
selects (CS
0
, CS
1
, CS
2
, and CS
3
) are used to independently
enable the four bytes. Two write enables (WE
0
and WE
1
) are
used to independently write to either the upper or lower 16-bit
word of RAM. Reading or writing can be executed on individual
bytes or on any combination of multiple bytes through the
proper use of selects and write enables.
Writing to each byte is accomplished when the appropriate
chip select (CS) and write enable (WE) inputs are both LOW.
Data on the input/output pins (I/O
X
) is written into the memory
location specified on the address pins (A
0
through A
17
).
Reading the device is accomplished by taking the chip selects
(CS) LOW, while write enables (WE) remain HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data input/output pins
(I/O).
The data input/output pins stay in the high-impedance state
when write enables (WE) are LOW or the appropriate chip
selects are HIGH.
Logic Block Diagram
Pin Configuration
1840–1
1840–2
DIP
Top View
I/O
10
I/O
11
0
I/O
31
I/O
30
I/O
29
I/O
28
V
CC
I/O
0
I/O
1
I/O
2
I/O
3
CS
0
A
1
I/O
4
I/O
5
I/O
6
I/O
7
A
2
A
3
WE
0
A
4
A
5
I/O
8
I/O
9
V
CC
CS
3
I/O
27
I/O
26
I/O
25
I/O
24
A
13
A
12
I/O
23
I/O
22
I/O
21
I/O
20
A
10
CS
2
I/O
19
I/O
18
I/O
17
I/O
16
A
17
A
16
A
11
A
9
A
15
A
14
WE
1
GND
A
0
A
17
WE
0
CS
0
CS
1
WE
1
CS
2
CS
3
I/O
0
I/O
3
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
18
4
4
4
4
4
4
4
4
I/O
4
I/O
7
I/O
8
I/O
11
I/O
12
I/O
15
I/O
16
I/O
19
I/O
20
I/O
23
I/O
24
I/O
27
I/O
26
I/O
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
40
39
38
37
41
42
43
44
45
46
50
49
48
47
51
52
53
54
55
56
60
59
58
57
A
6
A
7
A
8
CS
1
I/O
12
I/O
13
I/O
14
I/O
15
GND
Selection Guide
1840-20
20
1120
320
1840-25
25
1120
320
1840-30
30
1120
320
1840-35
35
1120
320
1840-45
45
1120
320
1840-55
55
1120
320
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
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