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參數(shù)資料
| 型號： | CYM1840 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 32 Static RAM Module(256K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 256K × 32靜態(tài)RAM模塊（256K × 32靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 123K |
| 代理商： | CYM1840 |
CYM1840
3
Switching Characteristics
Over the Operating Range
[3]
1840-20
1840-25
1840-30
Parameter
READ CYCLE
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACS
t
LZCS
t
HZCS
t
PU
t
PD
WRITE CYCLE
[6]
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
3.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
4.
At any given temperature and voltage condition, t
is less than t
for any given device.
5.
t
and t
are specified with C
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
6.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Read Cycle Time
20
25
30
ns
Address to Data Valid
20
25
30
ns
Output Hold from Address Change
5
5
5
ns
CS LOW to Data Valid
CS LOW to Low Z
[4]
CS HIGH to High Z
[4, 5]
20
25
30
ns
5
5
5
ns
20
20
20
ns
CS LOW to Power-Up
0
0
0
ns
CS HIGH to Power-Down
20
25
30
ns
Write Cycle Time
20
25
30
ns
CS LOW to Write End
18
20
25
ns
Address Set-Up to Write End
18
20
25
ns
Address Hold from Write End
2
2
2
ns
Address Set-Up to Write Start
2
2
2
ns
WE Pulse Width
15
20
25
ns
Data Set-Up to Write End
13
15
15
ns
Data Hold from Write End
2
2
2
ns
WE HIGH to Low Z
WE LOW to High Z
[5]
0
0
0
ns
0
15
0
15
0
15
ns
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