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參數(shù)資料
| 型號： | CYM1841A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 32 Static RAM Module(256K x 32 靜態(tài)RAM模塊) |
| 中文描述： | 256K × 32靜態(tài)RAM模塊（256K × 32靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 274K |
| 代理商： | CYM1841A |
256K x 32 Static RAM Module
fax id: 2017
CYM1841A
CYM1841C
Cypress Semiconductor Corporation
3901 North First Street
San Jose
September 1989 – Revised December 10, 1997
CA 95134
408-943-2600
Features
High-density 8-megabit SRAM module
32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
High-speed CMOS SRAMs
—Access time of 12 ns
Low active power
—5.3W (max.) at 25 ns
SMD technology
TTL-compatible inputs and outputs
Low profile
—Max. height of 0.58 in.
Available in ZIP, SIMM, and angled SIMM footprint
72-pin SIMM version compatible with 1M x 32
(CYM1851)
Functional Description
The CYM1841A/1841C are high-performance 8-megabit stat-
ic RAM modules organized as 256K words by 32 bits. This
module is constructed from eight 256K x 4 SRAMs in SOJ
packages mounted on an epoxy laminate board with pins. Four
chip selects (CS
1
, CS
2
, CS
3
, CS
4
) are used to independently
enable the four bytes. Reading or writing can be executed on
individual bytes or any combination of multiple bytes through
proper use of selects.
Writing to each byte is accomplished when the appropriate
chip select (CS) and write enable (WE) inputs are both LOW.
Data on the input/output pins (I/O) is written into the mem-
ory location specified on the address pins (A
0
through A
17
).
Reading the device is accomplished by taking the chip select
(CS) LOW while write enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pins will appear on the data input/output
pins (I/O).
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Two pins (PD
0
and PD
1
) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
The CYM1841A and CYM1841C are 100% pin, package, and
electrically identical. The CYM1841A utilizes corner power
and ground SRAMs, the CYM1841C utilizes center power and
ground SRAMs.
A 72-pin SIMM is offered for compatibility with the 1M x 32
CYM1851. This version is socket upgradable to the CYM1851.
Both the 64-pin and 72-pin SIMM modules are available with
either tin-lead or 10 micro-inches of gold flash on the edge
contacts.
Logic Block Diagram
1841A–1
A
0
–A
17
OE
WE
I/O
0
– I/O
3
CS
3
I/O
4
– I/O
7
CS
1
18
4
4
4
4
4
4
4
4
CS
2
CS
4
I/O
8
– I/O
11
I/O
16
– I/O
19
I/O
24
– I/O
27
I/O
12
– I/O
15
I/O
20
– I/O
23
I/O
28
– I/O
31
PD
0
– GND
PD
1
– GND
PD
2
– OPEN (72-pin only)
PD
3
– OPEN (72-pin only)
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
256K x 4
SRAM
相關(guān)PDF資料 |
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| CYM1851PM-12C | 1,024K x 32 Static RAM Module |
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| CYM1841AP5-45C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
| CYM1841AP6-15C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SRAM Module |
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