參數(shù)資料
型號: CYM1836V33
廠商: Cypress Semiconductor Corp.
英文描述: 128K x 32 3.3V Static RAM Module(128K x 32 3.3V 靜態(tài)RAM模塊)
中文描述: 128K的× 32 3.3靜態(tài)存儲器模塊(128K的× 32 3.3靜態(tài)內(nèi)存模塊)
文件頁數(shù): 3/7頁
文件大?。?/td> 260K
代理商: CYM1836V33
CYM1836V33
PRELIMINARY
3
AC Test Loads and Waveforms
1836V33–4
1836V33–5
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 481
R1 481
R2
255
R2
255
167
Equivalent to:
THé VENIN EQUIVALENT
1.73V
Switching Characteristics
Over the Operating Range
[4]
Parameter
READ CYCLE
t
RC
Description
1836V33–15
Min.
1836V33–20
Min.
1836V33–25
Min.
1836V33–30
Min.
1836V33–35
Min.
1836V33–45
Min.
Unit
Max.
Max.
Max.
Max.
Max.
Max.
Read Cycle
Time
Address to Data
Valid
Output Hold
from Address
Change
CS LOW to Data
Valid
OE LOW to Data
Valid
OE LOW to
Low Z
OE HIGH to
High Z
CS LOW to
Low Z
[5]
CS HIGH to High
Z
[5, 6]
15
20
25
30
35
45
ns
t
AA
15
20
25
30
35
45
ns
t
OHA
3
3
3
3
3
3
ns
t
ACS
15
20
25
30
35
45
ns
t
DOE
7
8
8
10
12
15
ns
t
LZOE
0
0
0
0
0
0
ns
t
HZOE
7
8
10
11
12
15
ns
t
LZCS
3
3
3
3
3
3
ns
t
HZCS
7
10
10
13
15
18
ns
Shaded area contains advance information.
Notes:
4.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±
500 mV from steady-state voltage.
5.
6.
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