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參數(shù)資料
| 型號： | CYD36S36V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
| 中文描述： | FullFlex器件特別提款權(quán)同步雙端口SRAM（FullFlex器件同步雙端口SRAM的特別提款權(quán)） |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 774K |
| 代理商： | CYD36S36V18 |
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FullFlex
Document #: 38-06082 Rev. *F
Page 16 of 52
Master Reset
The FullFlex family of Dual-Ports undergo a complete reset
when MRST is asserted. The MRST can be asserted
asynchronously to the clocks and must remain asserted for at
least t
RS
. Once asserted MRST deasserts READY, initializes
the internal burst counters, internal mirror registers, and
internal Busy Addresses to zero, and initializes the internal
mask register to all “1s”. All mailbox interrupts (INT), Busy
Address Outputs (BUSY), and burst counter interrupts
(CNTINT) are deasserted upon master reset. Releasing
MRST also signifies that the power supplies and all port clocks
are stable. This begins calibration of the DLL and VIM circuits.
READY will be asserted within 1024 clock cycles. READY is a
wired OR capable output with a strong pull-up and weak
Notes:
19.CE is internal signal. CE = LOW if CE
= LOW and CE
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the C and
can be deasserted after that. Data will be out after the following C edge and will be tri-stated after the next C edge.
20.OE is “Don’t Care” for mailbox operation.
21.At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
22.The “X” in this diagram represents the counter’s upper bits.
pull-down. Up to four outputs may be connected together. For
faster pull-down of the signal, connect a 250 Ohm resistor to
VSS. If the DLL and VIM circuits are disabled for a port, the
port will be operational within five clock cycles. However, the
READY will be asserted within 160 clock cycles.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates
using JEDEC-standard 3.3V or 2.5V I/O logic levels depending
on the VTTL power supply. It is composed of four input
connections and one output connection required by the test
logic defined by the standard.
2
20
2
19
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
20
2
19
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
20
2
19
2
6
2
1
2
5
2
2
2
4
2
3
2
0
2
20
2
19
2
6
2
1
2
5
2
2
2
4
2
3
2
0
H
H
L
H
1
1
0s
1
0
1
0
1
1
1
0
0
Xs
0
X
1
X
0
0
1
1
1
Xs
1
X
1
X
1
1
1
0
0
Xs
0
X
1
X
0
0
1
Masked Address
Unmasked Address
Mask
Register
LSB
Address
Counter
LSB
CNTINT
Example:
Load
Counter-Mask
Register = 00007F
Load
Address
Counter = 000005
Max
Address
Value
Max + 1
Address
Value
Figure 4. Programmable Counter-Mask Register Operation with WRP deasserted
[1, 22]
0
2
7
X
2
7
X
2
7
X
2
7
Table 9. Interrupt Operation Example
[1, 17, 19, 20, 21]
Function
Left Port
Right Port
R/W
L
L
CE
L
L
A
0L–20L
Max. Address
INT
L
X
R/W
R
X
CE
R
X
A
0R–20R
X
INT
R
L
Set Right INT
R
Flag
Reset Right INT
R
Flag
Set Left INT
L
Flag
Reset Left INT
L
Flag
X
X
X
X
H
L
Max. Address
H
X
X
X
L
L
L
Max. Address–1
X
H
L
Max. Address–1
H
X
X
X
X
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