參數(shù)資料
型號: CYD04S72V18
廠商: Cypress Semiconductor Corp.
英文描述: FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
中文描述: FullFlex器件特別提款權(quán)同步雙端口SRAM(FullFlex器件同步雙端口SRAM的特別提款權(quán))
文件頁數(shù): 17/52頁
文件大小: 774K
代理商: CYD04S72V18
FullFlex
Document #: 38-06082 Rev. *F
Page 17 of 52
Table 10.JTAG IDCODE Register Definitions
Part Number
CYD36S72V18
CYD36S36V18
CYD36S18V18
CYD18S72V18
CYD18S36V18
CYD18S18V18
CYD09S72V18
CYD09S36V18
CYD09S18V18
CYD04S72V18
CYD04S36V18
CYD04S18V18
Configuration
512Kx72
1024Kx36
2048Kx36
256Kx72
512Kx36
1024Kx18
128Kx72
256Kx36
512Kx18
64Kx72
128Kx36
256Kx18
Value
0C026069h (x2)
0C023069h
0C024069h
0C025069h
0C026069h
0C027069h
0C028069h
0C029069h
0C02A069h
0C02B069h
0C02C069h
0C02D069h
Table 11.Scan Registers Sizes
Register Name
Instruction
Bypass
Identification
Boundary Scan
Bit Size
4
1
32
n
[23]
Table 12.Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
Code
Description
0000
1111
1011
0111
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers
to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Other combinations are reserved. Do not use other than the above.
CLAMP
SAMPLE/PRELOAD
RESERVED
0100
1000
All other codes
Note:
23.Details of the boundary scan length can be found in the BSDL file for the device.
相關(guān)PDF資料
PDF描述
CYD36S72V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD09S72V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD36S18V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD36S36V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
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