參數(shù)資料
型號(hào): CYD04S72V18
廠商: Cypress Semiconductor Corp.
英文描述: FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
中文描述: FullFlex器件特別提款權(quán)同步雙端口SRAM(FullFlex器件同步雙端口SRAM的特別提款權(quán))
文件頁(yè)數(shù): 13/52頁(yè)
文件大?。?/td> 774K
代理商: CYD04S72V18
FullFlex
Document #: 38-06082 Rev. *F
Page 13 of 52
Notes:
17.“X” = “Don’t Care”, “H” = HIGH, “L” = LOW.
18.Counter operation and mask register operation is independent of chip enables.
Table 8. Burst Counter and Mask Register Control Operation (Any Port)
[17, 18]
C
MRST
CNTRST
CNT/MSK
CNTEN
ADS
RET
Operation
Description
X
L
X
X
X
X
X
Master Reset
Reset address counter to all 0s, mask register
to all 1s, and busy address to all 0’s.
H
L
H
X
X
X
Counter Reset Reset counter and mirror unmasked portion to
all 0s.
H
L
L
X
X
X
Mask Reset
Reset mask register to all 1s.
H
H
H
L
L
X
Counter Load
Load burst counter and mirror with external
address value presented on address lines.
H
H
L
L
L
X
Mask Load
Load mask register with value presented on the
address lines.
H
H
H
L
H
L
Retransmit
Load counter with value in the mirror register
H
H
H
L
H
H
Counter
Increment
Internally increment address counter value.
H
H
H
H
H
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
H
H
H
H
L
H
Counter
Readback
Read out counter internal value on address
lines.
H
H
L
H
L
H
Mask
Readback
Read out mask register value on address lines.
H
H
L
H
H
L
Busy Address
Readback
Read out first busy address after last busy
address readback
H
H
L
L
H
X
Reserved
H
H
L
H
L
L
Reserved
H
H
L
H
H
H
Reserved
H
H
H
H
L
L
Reserved
H
H
H
H
H
L
Reserved
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