參數(shù)資料
型號： CY8C22213-24PVIT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO20
封裝： 0.210 INCH, SSOP-20
文件頁數(shù)： 267/304頁
文件大?。?/td> 2956K
代理商： CY8C22213-24PVIT
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December 22, 2003
Document No. 38-12009 Rev. *D
267
CY8C22xxx Preliminary Data Sheet
26. I2C
26.3.2
I2C_SCR Register
This register is the I2C status and control register and is
used to control both Master and Slave data transfer. It con-
tains status bits for determining the state of the current I2C
transfer, and control bits, which determine the actions for the
next byte transfer. At the end of each byte transfer, the I2C
hardware will interrupt the host processor and stall the bus
on the subsequent low of the clock until the host intervenes
with the next command. This register may be read as many
times as necessary, but on a subsequent write, the bus stall
will be released and the current transfer will continue.
There are six status bits: Byte Complete, LRB, Address,
Stop Status, Lost Arb, and Bus Error. These bits have Read/
Clear (R/C) access, which means that they are set by hard-
ware but may be cleared by a write of ‘0’ to the bit position.
Under certain conditions, status is cleared automatically by
the hardware. These cases are noted in
Table 26-5
.
There are two control bits: Transmit and ACK. These bits
have R/W access. These bits may also be cleared by hard-
ware, as noted.
Bit 7: Bus Error.
The Bus Error status detects misplaced
Start or Stop conditions on the bus. These may be due to
noise, rogue devices, or other devices that are not yet syn-
chronized with the I2C bus traffic. According to the I2C
specification mentioned previously, all compatible devices
must reset their interface on a received Start or Stop. This is
a natural thing to do in Slave mode, because a Start will ini-
tiate an address reception and a Stop will idle the Slave. In
the case of a Master, this event will force the Master to
release the bus and idle. However, since a Master does not
respond to external Start or Stop conditions, an immediate
interrupt on this event allows the Master to continue to keep
track of the bus state.
A bus error is defined as follows. A Start is only valid if the
block is idle (Master or Slave) or a Slave receiver is ready to
receive the first bit of a new byte after an ACK. Any other
timing for a Start condition causes the Bus Error bit to be
set. A Stop is only valid if the block is idle or a Slave receiver
is ready to receive the first bit of a new byte after an ACK.
Any other timing for a Stop condition causes the Bus Error
bit to be set.
Bit 6: Lost Arb.
This bit is set when I2C bus contention is
detected, during a Master mode transfer. Contention will
occur when a Master is writing a ‘1’ to the SDA output line
and reading back a ‘0’ on the SDA input line at given sam-
pling point. When this occurs, the block immediately
releases the SDA, but continues clocking to the end of the
current byte. On the resulting byte interrupt, firmware can
determine that arbitration was lost to another master.
Table 26-5. I2C_SCR Status and Control
Register
Bit
0
Access
R/C
Description
Byte Complete
Transmit Mode:
1 = 8 bits of data have been transmitted
and an ACK or NACK has been received.
Receive Mode:
1 = 8 bits of data have been received.
Any Start detect will automatically clear
this bit.
LRB
Last Received Bit. The value of the 9
th
bit
in a Transmit sequence, which is acknowl-
edge bit from the receiver.
0 = Last transmitted byte was ACKed by
the receiver.
1 = Last transmitted byte was NACKed by
the receiver.
Any Start detect will automatically clear
this bit.
Transmit
0 = Receive Mode.
1 = Transmit Mode.
This bit is set by firmware to define the
direction of the byte transfer.
Any Start detect will automatically clear
this bit.
Address
1 = The transmitted or received byte is an
address.
This status bit must be cleared by firmware
with write of ‘0’ to the bit position.
Mode
Master/
Slave
1
R/C
Master/
Slave
2
R/W
Master/
Slave
3
R/C
Master/
Slave
4
R/W
ACK
Acknowledge Out
0 = NACK the last received byte.
1 = ACK the last received byte.
This bit is automatically cleared by hard-
ware on the following Byte Complete
event.
Stop Status
1 = A Stop condition was detected.
This status bit must be cleared by firmware
with write of ‘0’ to the bit position. It is
never cleared by the hardware.
Lost Arb
1 = Lost Arbitration.
This bit is set immediately on lost arbitra-
tion; however, it does not cause an inter-
rupt. This status may be checked after the
following Byte Complete interrupt.
Any Start detect will automatically clear
this bit.
Bus Error
1 = A misplaced Start or Stop condition
was detected.
This status bit must be cleared by firmware
with write of ‘0’ to the bit position. It is
never cleared by the hardware.
Master/
Slave
5
R/C
Master/
Slave
6
R/C
Master
Only
7
R/C
Master
Only
Table 26-5. I2C_SCR Status and Control
Register
(continued)
Bit
Access
Description
Mode
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