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參數(shù)資料
| 型號： | CY8C22213-24PVIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO20 |
| 封裝： | 0.210 INCH, SSOP-20 |
| 文件頁數(shù)： | 226/304頁 |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22213-24PVIT |
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18. Analog Interface
CY8C22xxx Preliminary Data Sheet
226
Document No. 38-12009 Rev. *D
December 22, 2003
18.1.4
Decimator and Incremental ADC
Interface
The Decimator and Incremental interface provides hardware
support and signal routing for analog-to-digital conversion
functions, specifically the Delta-Signal ADC and the Incre-
mental ADC. The control signals for this interface is split
between two registers: DEC_CR0 and DEC_CR1.
18.1.4.1
Decimator
The decimator is a hardware block that is used to perform
digital processing on the analog block outputs. The DCLKS0
and DCLKS1 bits, which are split between the DEC_CR0
and DEC_CR1 registers, are used to select a source for the
Decimator output latch enable. The Decimator is typically
run autonomously over a given period. The length of this
period is set in a Timer block that is running in conjunction
with the analog processing. At the terminal count of this
Timer, the primary output goes high for a one-half clock
cycle. For purposes of Decimator operation, this signal is
inverted and connected to the BW input. This becomes the
output latch enable signal, which transfers data from the
internal accumulators to an output buffer. The terminal count
also causes an interrupt and the CPU may read this output
buffer at any time between one latch event and the next.
18.1.4.2
Incremental ADC
The analog interface has support for the incremental ADC
operation through the ability to gate the analog comparator
outputs. This gating function is required in order to precisely
control the digital integration period that is performed in a
digital block, as part of the function. A digital block PWM is
used as a source to provide the gate signal. Only one
source for the gating signal can be selected. However, the
gating can be applied independently to any of the column
comparator outputs.
The ICLKS0 and ICLKS1 bits, which are split between the
DEC_CR0 and DEC_CR1 registers, are used to select a
source for the incremental gating signal. The four IGEN bits
are used to independently enable the gating function on a
column-by-column basis.
18.1.5
Analog Modulator Interface (Mod
Bits)
The Analog Modulator Interface provides a selection of sig-
nals that are routed to any of the four analog array modula-
tion control signals. There is one modulation control signal
for each Type C Analog Switched Capacitor block in every
analog column. There are eight selections, which include
the analog comparator bus outputs, two global outputs, and
a digital block broadcast bus. The selections for all columns
are identical and are contained in the AMD_CR0 and
AMD_CR1 registers. The Mod bit is XOR’ed with the
Switched Capacitor block Sign bit (ASign in ASCxxCR0) to
provide dynamic control of that bit.
18.1.6
Analog Synchronization Interface
(Stalling)
For high precision analog operation, it is necessary to pre-
cisely time when updated register values are available to the
analog PSOC blocks. The optimum time to update values in
Switch Cap registers is at the beginning of the PHI1 active
period. Depending on the relationship between the CPU
CLK and the analog column clock, the CPU IO write cycle
can occur at any 24 MHz master clock boundary in the PHI1
or PHI2 cycle. Register values may be written at arbitrary
times; however, glitches may be apparent at analog outputs.
This is because the capacitor value is changing when the
circuit is designed to be settling.
The SYNCEN bit in the Analog Synchronization Control
Register (ASY_CR) is designed to address this problem.
When the SYNCEN bit is set, an IO write instruction to any
Switch Cap registers is blocked at the interface and the CPU
will stall. On the subsequent rising edge of PHI1, the CPU
stall is released, allowing the IO write to be performed at the
destination analog register. This mode synchronizes the IO
write action to be performed at the optimum point in the ana-
log cycle, at the expense of CPU bandwidth.
Figure 18-4
shows the timing for this operation.
Figure 18-4. Synchronized Write to a DAC Register
As an alternative to stalling, the source for the analog col-
umn interrupts is set as the falling edge of the PHI2 clock.
This configuration synchronizes the CPU to perform the IO
write after the PHI2 phase is completed, which is equivalent
to the start of PHI1.
18.1.7
SAR Hardware Acceleration
The SAR algorithm is a binary search on the DAC code that
best matches the input voltage that is being measured. The
first step is to take an initial guess at mid-scale, which effec-
tively splits the range by half. The DAC output value is then
compared to the input voltage. If the guess is too low, a
result bit is set for that binary position and the next guess is
set at mid-scale of the remaining upper range. If the guess
is too high, a result bit is cleared and the next guess is set at
mid-scale of the remaining lower range. This process is
repeated until all bits are tested. The resulting DAC code is
CPUCLK
(Generated)
CPUCLK
(To CPU)
IOW
STALL
PHI
CLK24
AIOW
Stall is released here.
AIOW
completes here.
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參數(shù)描述 |
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| CY8C22213-24SI | 功能描述:IC MCU 2K FLASH 256B 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設(shè)備:電容感應(yīng)，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤 |
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| CY8C22345 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip |
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