參數(shù)資料
型號： CY8C21323
廠商： Cypress Semiconductor Corp.
英文描述： PSoC Mixed-Signal Array(PSoC混合信號陣列)
中文描述： PSoC混合信號陣列（的PSoC混合信號陣列）
文件頁數(shù)： 27/33頁
文件大小： 325K
代理商： CY8C21323
February 25, 2005
Document No. 38-12022 Rev. *G
27
CY8C21x23 Final Data Sheet
3. Electrical Specifications
3.4.6
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25
°
C
and are for design guidance only.
3.4.7
AC I
2
C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, or 2.4V to 3.0V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25
°
C and are for design guidance only.
Table 3-24. AC Programming Specifications
Symbol
T
RSCLK
T
FSCLK
T
SSCLK
T
HSCLK
F
SCLK
T
ERASEB
T
WRITE
T
DSCLK3
T
DSCLK2
Description
Min
Typ
Max
Units
ns
Notes
Rise Time of SCLK
1
–
20
Fall Time of SCLK
1
–
20
ns
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
Data Hold Time from Falling Edge of SCLK
40
–
–
ns
Frequency of SCLK
0
–
8
MHz
Flash Erase Time (Block)
–
15
–
ms
Flash Block Write Time
–
30
–
ms
Data Out Delay from Falling Edge of SCLK
–
–
50
ns
3.0
≤
Vdd
≤
3.6
2.4
≤
Vdd
≤
3.0
Data Out Delay from Falling Edge of SCLK
–
–
70
ns
Table 3-25. AC Characteristics of the I
2
C SDA and SCL Pins for Vcc
≥
3.0V
Symbol
F
SCLI2C
T
HDSTAI2C
Description
Standard Mode
Min
Fast Mode
Min
Units
kHz
Notes
Max
Max
SCL Clock Frequency
0
100
0
400
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
LOW Period of the SCL Clock
4.0
–
0.6
–
μ
s
T
LOWI2C
T
HIGHI2C
T
SUSTAI2C
T
HDDATI2C
T
SUDATI2C
T
SUSTOI2C
T
BUFI2C
T
SPI2C
4.7
–
1.3
–
μ
s
μ
s
μ
s
μ
s
HIGH Period of the SCL Clock
4.0
–
0.6
–
Set-up Time for a Repeated START Condition
4.7
–
0.6
–
Data Hold Time
0
–
0
–
Data Set-up Time
0
Set-up Time for STOP Condition
250
0
4.0
–
0
–
100
a
0.6
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system but the requirement t
SU;DAT
≥
250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
–
0
–
ns
0
μ
s
μ
s
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
Pulse Width of spikes are suppressed by the input filter.
–
–
0
50
ns
相關(guān)PDF資料
PDF描述
CY8C21123 PSoC Mixed-Signal Array(PSoC混合信號陣列)
CY8C21223 PSoC Mixed-Signal Array(PSoC混合信號陣列)
CY8C21634-24AX PSoC Mixed-Signal Array
CY8C21534 PSoC Mixed-Signal Array
CY8C21234-24LFX PQ I HIP6W DUET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY8C21323_06 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC㈢ Mixed-Signal Array
CY8C21323_08 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC? Mixed Signal Array
CY8C21323-12PVXE 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC㈢ Mixed-Signal Array
CY8C21323-12PVXET 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC㈢ Mixed-Signal Array
CY8C21323-24LFXI 功能描述:可編程片上系統(tǒng) - PSoC IC MCU 4K FLASH 256B SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*