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參數(shù)資料
| 型號： | CY7C63231A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | enCoRe USB Low-speed USB Peripheral Controller(enCoRe USB 低速USB外設(shè)控制器) |
| 中文描述： | 的enCoRe USB低速USB外設(shè)控制器（的enCoRe的USB低速的USB外設(shè)控制器） |
| 文件頁數(shù)： | 27/50頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | CY7C63231A |
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FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *B
Page 27 of 50
Bit [3:0]: Mode Bit [3:0]
The EP1 Mode Bits operate in the same manner as the EP0 Mode Bits (see Section 14.2).
14.4
There are two Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in
Figure 14-4
.
USB Endpoint Counter Registers
Bit 7: Data Toggle
This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the transmitted
Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
1 = DATA1
0 = DATA0
Bit 6: Data Valid
This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuff, or PID errors have occurred. This
bit does not update for some endpoint mode settings. Refer to
Table 20-3
for more details.
1 = Data is valid.
0 = Data is invalid. If enabled, the endpoint interrupt will occur even if invalid data is received.
Bit [5:4]:
Reserved
Bit [3:0]: Byte Count Bit [3:0]
Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the
number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP
transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values
are 2 to 10 inclusive.
For Endpoint 0 Count Register, whenever the count updates from a SETUP or OUT transaction, the count register locks and
cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on
incoming SETUP or OUT transactions before firmware has a chance to read the data.
15.0
USB Regulator Output
The VREG pin provides a regulated output for connecting the pull-up resistor required for USB operation. For USB, a 1.5-k
resistor is connected between the D– pin and the VREG voltage, to indicate low-speed USB operation. Since the VREG output
has an internal series resistance of approximately 200
, the external pull-up resistor required is R
PU
(see Section 23.0).
The regulator output is placed in a high-impedance state at reset, and must be enabled by firmware by setting the VREG Enable
bit in the USB Status and Control Register (
Figure 13-1
). This simplifies the design of a combination PS/2-USB device, since the
USB pull-up resistor can be left in place during PS/2 operation without loading the PS/2 line. In this mode, the VREG
pin can be
used as an input and its state can be read at port P2.0. Refer to
Figure 12-8
for the Port 2 data register. This input has a TTL
threshold.
In suspend mode, the regulator is automatically disabled. If VREG Enable bit is set (
Figure 13-1
), the VREG pin is pulled up to
V
CC
with an internal 6.2-k
resistor. This holds the proper V
OH
state in suspend mode.
Note that enabling the device for USB (by setting the Device Address Enable bit,
Figure 14-1
) activates the internal regulator,
even if the VREG Enable bit is cleared to 0. This insures proper USB signaling in the case where the VREG pin is used as an
input, and an external regulator is provided for the USB pull-up resistor. This also limits the swing on the D– and D+ pins to about
1V above the internal regulator voltage, so the Device Address Enable bit normally should only be set for USB operating modes.
The regulator output is only designed to provide current for the USB pull-up resistor. In addition, the output voltage at the VREG
pin is effectively disconnected when the device transmits USB from the internal SIE. This means that the VREG pin does not
provide a stable voltage during transmits, although this does not affect USB signaling.
Bit #
7
6
5
4
3
2
1
0
Bit Name
Data Toggle
Data Valid
Reserved
Byte Count
Read/Write
R/W
R/W
-
-
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Figure 14-4. Endpoint 0 and 1 Counter Registers (Addresses 0x11 and 0x13)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63231A-PXC | 功能描述:8位微控制器 -MCU enCoRe RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C63231A-SC | 功能描述:IC MCU 3K USB LS PERIPH 18-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63231A-SXC | 功能描述:8位微控制器 -MCU enCoRe RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CY7C63231A-SXCT | 功能描述:IC MCU 3K USB LS PERIPH 18-SOIC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
| CY7C63310-PXC | 功能描述:USB 接口集成電路 USB 3K Flash 128 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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