參數(shù)資料
型號(hào)： CY7C63231-PC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： enCoRe USB Low-speed USB Peripheral Controller
中文描述： 8-BIT, OTPROM, RISC MICROCONTROLLER, PDIP18
封裝： 0.300 INCH, PLASTIC, DIP-18
文件頁(yè)數(shù)： 25/49頁(yè)
文件大小： 960K
代理商： CY7C63231-PC
FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *A
Page 25 of 49
14.0
USB Device
The CY7C632XX supports one USB Device Address with two endpoints: EP0 and EP1.
14.1
The USB Device Address Register contains a 7-bit USB address and one bit to enable USB communication. This register is
cleared during a reset, setting the USB device address to zero and marking this address as disabled.
Figure 14-1
shows the
format of the USB Address Register.
USB Address Register
In either USB or PS/2 mode, this register is cleared by both hardware resets and the USB bus reset. See Section 19.3 for more
information on the USB Bus Reset - PS/2 interrupt.
Bit 7: Device Address Enable
This bit must be enabled by firmware before the serial interface engine (SIE) will respond to USB traffic at the address specified
in Bit [6:0].
1 = Enable USB device address.
0 = Disable USB device address.
Bit [6:0]: Device Address Bit[6:0]
These bits must be set by firmware during the USB enumeration process (i.e., SetAddress) to the non-zero address assigned
by the USB host.
14.2
All USB devices are required to have an endpoint number 0 (EP0) that is used to initialize and control the USB device. EP0
provides access to the device configuration information and allows generic USB status and control accesses. EP0 is bidirectional,
as the device can both receive and transmit data. EP0 uses an 8-byte FIFO at SRAM locations 0xF8-0xFF, as shown in
Section 8.2.
The EP0 endpoint mode register uses the format shown in
Figure 14-2
.
USB Control Endpoint
The SIE provides a locking feature to prevent firmware from overwriting bits in the USB Endpoint 0 Mode Register. Writes to the
register have no effect from the point that Bit[6:0] of the register are updated (by the SIE) until the firmware reads this register.
The CPU can unlock this register by reading it.
Because of these hardware-locking features, firmware should perform an read after a write to the USB Endpoint 0 Mode Register
and USB Endpoint 0 Count Register (
Figure 14-4
) to verify that the contents have changed as desired, and that the SIE has not
updated these values.
Bit [7:4] of this register are cleared by any non-locked write to this register, regardless of the value written.
Bit 7: SETUP Received
1 = A valid SETUP packet has been received. This bit is forced HIGH from the start of the data packet phase of the SETUP
transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval.
Bit #
Bit Name
7
6
5
4
3
2
1
0
Device
Address
Enable
R/W
0
Device Address Bit
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 14-1. USB Device Address Register (Address 0x10)
Bit #
Bit Name
7
6
IN
5
4
3
2
1
0
SETUP
Received
R/W
0
Received
R/W
0
OUT
Received
R/W
0
ACKed
Transaction
R/W
0
Mode Bit
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Figure 14-2. Endpoint 0 Mode Register (Address 0x12)
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