參數(shù)資料
型號: CY7C63231-PC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: enCoRe USB Low-speed USB Peripheral Controller
中文描述: 8-BIT, OTPROM, RISC MICROCONTROLLER, PDIP18
封裝: 0.300 INCH, PLASTIC, DIP-18
文件頁數(shù): 19/49頁
文件大小: 960K
代理商: CY7C63231-PC
FOR
FOR
enCoRe
USB
CY7C63221/31A
Document #: 38-08028 Rev. *A
Page 19 of 49
12.0
General Purpose I/O Ports
Ports 0 and 1 provide up to 10 versatile GPIO pins that can be read or written (the number of pins depends on package type).
Figure 12-1. Block Diagram of GPIO Port (one pin shown)
Port 0 is an 8-bit port; Port 1 contains 2 bits, P1.1
P1.0 in the CY7C63231 and CY7C63221A-XC parts. Each bit can also be
selected as an interrupt source for the microcontroller.
The data for each GPIO pin is accessible through the Port Data Register. Writes to the Port Data Register store outgoing data
state for the port pins, while reads from the Port Data Register return the actual logic value on the port pins, not the Port Data
Register contents.
Each GPIO pin is configured independently. The driving state of each GPIO pin is determined by the value written to the pin
s
Data Register and by two associated pin
s Mode0 and Mode1 bits.
The Port 0 Data Register is shown in
Figure 12-2
, and the Port 1 Data Register is shown in
Figure 12-3
. The Mode0 and Mode1
bits for the two GPIO ports are given in
Figure 12-4
through
Figure 12-7
.
Bit [7:0]: P0[7:0]
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit #
Bit Name
Read/Write
Reset
7
6
5
4
3
2
1
0
P0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Figure 12-2. Port 0 Data (Address 0x00)
GPIO
Pin
V
CC
14 k
GPIO
Mode
Data
Out
Register
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Logic
C
To Interrupt
Controller
Q1
Q2
Q3
Interrupt
Polarity
2
Threshold Select
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CY7C63231A-SC enCoRe USB Low-speed USB Peripheral Controller
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CY7C63221A-PC enCoRe USB Low-speed USB Peripheral Controller
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CY7C63231A enCoRe USB Low-speed USB Peripheral Controller(enCoRe USB 低速USB外設(shè)控制器)
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