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參數(shù)資料
| 型號： | CY7C454 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時(shí)的先進(jìn)先出) |
| 中文描述： | 4Kx9級聯(lián)與時(shí)鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的4Kx9可級聯(lián)定時(shí)的先進(jìn)先出） |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C454 |
CY7C451
CY7C453
CY7C454
6
PRELIMINARY
t
SKEW2[16]
t
PMR
t
SCMR
t
OHMR
t
MRR
Opposite Clock Before Clock
12
14
20
30
ns
Master Reset Pulse Width (MR LOW)
12
14
20
30
ns
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
0
ns
Data Hold From MR LOW
0
0
0
0
ns
Master Reset Recovery
(MR HIGH Set-Up to First Enabled
Write/Read)
12
14
20
30
ns
t
MRF
t
AMR
t
SMRP
t
HMRP
t
FTP
t
AP
t
OHP
MR HIGH to Flags Valid
12
14
20
30
ns
MR HIGH to Data Outputs LOW
12
14
20
30
ns
Program Mode—MR LOW Set-Up
12
14
20
30
ns
Program Mode—MR LOW Hold
9
10
15
25
ns
Program Mode—Write HIGH to Read HIGH
12
14
20
30
ns
Program Mode—Data Access Time
12
14
20
30
ns
Program Mode—Data Hold Time from MR
HIGH
0
0
0
0
ns
t
PRT
t
RTR
16. t
is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than t
before the clock, the decision of whether or not to include the opposite clock in the
current clock cycle is arbitrary. See Note 15 for definition of clock and opposite clock.
Retransmit Pulse Width
12
14
20
30
Retransmit Recovery Time
12
14
20
30
Switching Characteristics
Over the Operating Range
[12]
(continued)
Parameter
Description
7C451-12
7C453-12
7C454-12
Min.
7C451-14
7C453-14
7C454-14
Min.
7C451-20
7C453-20
7C454-20
Min.
7C451-30
7C453-30
7C454-30
Min.
Unit
Max.
Max.
Max.
Max.
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|---|---|
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