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參數(shù)資料
| 型號： | CY7C454 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的4Kx9可級聯(lián)定時的先進先出) |
| 中文描述： | 4Kx9級聯(lián)與時鐘FIFO的可編程標志（帶可編程標記的4Kx9可級聯(lián)定時的先進先出） |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C454 |
CY7C451
CY7C453
CY7C454
17
PRELIMINARY
Flag Operation
(continued)
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the flags signifying fullness (Half
Full, Almost Full, Full) are exclusively updated by CKW, careful
attention must be given to the flag operation. The user must
be aware that if a boundary (Empty, Almost Empty, Half Full,
Almost Full, or Full) is crossed due to an operation from a clock
that the flag is not synchronized to (i.e., CKW does not affect
Empty or Almost Empty), a flag update cycle is necessary to
represent the FIFO’s new state. The signal to which a flag is
not synchronized will be referred to as the opposite clock
(CKW is opposite clock for Empty and Almost Empty flags;
CKR is the opposite clock for Half Full, Almost Full, and Full
flags). Until a proper flag update cycle is executed, the syn-
chronous flags will not show the new state of the FIFO.
When updating flags, the CY7C451/453/454 must make a de-
cision as to whether or not the opposite clock was recognized
when a clock updates the flag. For example (when updating
the Empty flag), if a write occurs at least t
SKEW1
after a read,
the write is guaranteed not to be included when CKR up-
dates the flag. If a write occurs at least t
SKEW2
before a
read, the write is guaranteed to be included when CKR
updates flag. If a write occurs within t
SKEW1
/t
SKEW2
after or
before CKR, then the decision of whether or not to include
the write when the flag is updated by CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Half
Full, Almost Full) is different from that used to update the
boundary flags (Empty, Full). Both operations are described
below.
Boundary and Non-Boundary Flags
Boundary Flags (Empty)
The Empty flag is synchronized to the CKR signal (i.e., the
Empty flag can only be updated by a clock pulse on the CKR
pin). An empty FIFO that is written to will be described with an
Empty flag state until a rising edge is presented to the CKR
pin. When making the transition from Empty to Almost Empty
(or Empty to Less than or Equal to Half Full), a clock cycle on
the CKR is necessary to update the flags to the current state.
In such a state (flags showing Empty even though data has
been written to the FIFO), two read cycles are required to read
data out of FIFO. The first read serves only to update the flags
to the Almost Empty or Less than or Equal to Half Full state,
while the second read outputs the data. This first read cycle is
known as the latent or flag update cycle because it does not
affect the data in the FIFO or the count (number of words in
FIFO). It simply deasserts the Empty flag. The flag is updated
regardless of the ENR state. Therefore, the update occurs
even when ENR is unasserted (HIGH), so that a valid read
is not necessary to update the flags to correctly describe
the FIFO. In this example, the write must occur at least
t
SKEW2
before the flag update cycle in order for the FIFO to
guarantee that the write will be included in the count when
CKR updates the flags. When a free-running clock is con-
nected to CKR, the flag is updated each cycle. Table 2
shows an example of a sequence of operations that update
the Empty flag.
Table 1. Flag Truth Table
[45]
E/F
0
1
1
PAFE
0
0
1
HF
1
1
1
State
Empty
CY7C451 512 x 9
Number of Words
in FIFO
0
1
(16
P)
(16
P)+1
256
CY7C453 2K x 9
Number of Words
in FIFO
0
1
(16
P)
(16
P)+1
1024
CY7C454 4K x 9
Number of Words
in FIFO
0
1
(16
P)
(16
P)+1
2048
Almost Empty
Less than or
Equal to Half Full
Greater than Half
Full
Almost Full
Full
1
1
0
257
511
(16
P)
1025
2047
(
16
P)
2049
4095
(
16
P)
1
0
0
0
0
0
512
(16
P)
511
512
2048
(16
P)
2047 4096
(16
P)
4095
2048
4096
Note:
45. P is the decimal value of the binary number represented by D
. When programming the CY7C451/453/454, P can have values from 0 to 15 for the
CY7C451 and values from 0 to 63 for the CY7C453 and CY7C454. See Table 5 or D
0 - 5
representation. P = 0 signifies Almost Empty state = Empty
state.
Figure 1. Flag Logic Diagram
D Q
CKR
E
D Q
CKW
F
D Q
CKR
PAE
D Q
CKW
PAF
D Q
CKW
HF
INTERNAL LOGIC
HF
PAFE
E/F
PIN
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相關代理商/技術參數(shù) |
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