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參數(shù)資料
| 型號： | CY7C454 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的4Kx9可級聯(lián)定時的先進先出) |
| 中文描述： | 4Kx9級聯(lián)與時鐘FIFO的可編程標志（帶可編程標記的4Kx9可級聯(lián)定時的先進先出） |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C454 |
CY7C451
CY7C453
CY7C454
4
PRELIMINARY
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Output HIGH
Voltage
Output LOW
Voltage
Test Conditions
V
CC
= Min., I
OH
=
2.0 mA
7C451-12
7C453-12
7C454-12
Min.
2.4
7C451-14
7C453-14
7C454-14
Min.
2.4
7C451-20
7C453-20
7C454-20
Min.
2.4
7C451-30
7C453-30
7C454-30
Min.
2.4
Max.
Max.
Max.
Max.
Unit
V
V
OL
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH[1]
V
IL[1]
I
IX
Input HIGH Voltage
Input LOW Voltage
2.2
0.5
10
V
CC
0.8
2.2
0.5
10
V
CC
0.8
2.2
0.5
10
V
CC
0.8
2.2
0.5
10
V
CC
0.8
V
V
μ
A
Input Leakage
Current
Output Short
Circuit Current
V
CC
= Max.
+10
+10
+10
+10
I
OS[2]
V
CC
= Max., V
OUT
= GND
90
90
90
90
mA
I
OZL
I
OZH
I
CC1[3]
Output OFF, High Z
Current
OE > V
IH
, V
SS
< V
O
< V
CC
10
+10
10
+10
10
+10
10
+10
μ
A
Operating Current
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
140
140
120
100
mA
Mil/Ind
Com’l
150
70
150
70
130
70
110
70
mA
mA
I
CC2[4]
Operating Current
V
CC
= Max.,
I
OUT
= 0 mA
Mil/Ind
80
80
80
80
mA
I
SB[5]
Standby Current
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Mil/Ind
30
30
30
30
30
30
30
30
mA
mA
Capacitance
[6]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
12
Unit
pF
pF
C
IN
C
OUT
Notes:
1.
2.
3.
Input Capacitance
Output Capacitance
The V
and V
specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V
SS
.
Test no more than one output at a time for not more than one second.
Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (f
MAX
), while data inputs
switch at f
/2. Outputs are unloaded.
Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
All input signals are connected to V
. All outputs are unloaded. Read and write clocks switch at maximum frequency (f
MAX
).
Tested initially and after any design or process changes that may affect these parameters.
4.
5.
6.
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