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參數(shù)資料
| 型號(hào)： | CY7C451 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| 中文描述： | 512x9級(jí)聯(lián)與時(shí)鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的512x9可級(jí)聯(lián)定時(shí)的先進(jìn)先出） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C451 |
CY7C451
CY7C453
CY7C454
9
PRELIMINARY
Notes:
21. “Count” is the number of words in the FIFO.
22. The FIFO is assumed to be programmed with P>0 (i.e., PAFE does not transition at Empty or Full).
23. R2 is ignored because the FIFO is empty (count = 0). It is important to note that R3 is also ignored because W3, the first enabled write after empty, occurs
less than t
before R3. Therefore, the FIFO still appears empty when R3 occurs. Because W3 occurs greater than t
SKEW2
before R4, R4 includes
W3 in the flag update.
24. CKR is clock; CKW is opposite clock.
25. R3 updates the flag to the Empty state by asserting E/F. Because W1 occurs greater than t
after R3, R3 does not recognize W1 when updating
flag status. But because W1 occurs greater than t
before R4, R4 includes W1 in the flag update and, therefore, updates FIFO to Almost Empty
state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status regardless of the state of ENR. It does not change the count
or the FIFO’s data outputs.
Switching Waveforms
(continued)
Read to Empty Timing Diagram with Free-Running Clocks
LATENTCYCLE
t
SKEW1
t
SKEW2
t
FD
t
FD
t
FD
COUNT
1
0
1
0
EREAD
FLAG
READ
EREAD
IREAD
EWRITE
IREAD
IREAD
t
SKEW2
CKR
ENR
CKW
ENW
PAFE
E/F
HF
C451-11
HIGH
LOW
Read to Empty Timing Diagram
COUNT
3
2
0
1 (NO CHANGE)
t
FD
t
FD
ENR1
READ
FR4
READ
1
1
0
LATENTCYCLE
EWRITE
t
SKEW2
t
SKEW1
CKW
ENR
ENW
E/F
CKR
LOW
t
FD
C451-12
ENR2
READ
ENR3
READ
ENR5
READ
W1
R1
R2
R3
R4
R5
R6
W1
W2
W4
W5
W6
W3
PAFE
LOW
[21,24,25]
[21,22,23,24]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級(jí)聯(lián)的 64K x9 先進(jìn)先出) |
| CY7C460A | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JI | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C451-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C451-30LMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C453 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-14JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
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