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參數(shù)資料
| 型號： | CY7C451 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的512x9可級聯(lián)定時的先進先出) |
| 中文描述： | 512x9級聯(lián)與時鐘FIFO的可編程標志（帶可編程標記的512x9可級聯(lián)定時的先進先出） |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 437K |
| 代理商： | CY7C451 |
CY7C451
CY7C453
CY7C454
5
PRELIMINARY
AC Test Loads and Waveforms
[7, 8, 9, 10, 11]
Switching Characteristics
Over the Operating Range
[12]
Parameter
t
CKW
t
CKR
t
CKH
t
CKL
t
A[13]
t
OH
t
FH
t
SD
t
HD
t
SEN
t
HEN
t
OE
t
OLZ[6,14]
t
OHZ[6,14]
t
PG
t
PE
t
FD
t
SKEW1[15]
Notes:
7.
C
L
= 30 pF for all AC parameters except for t
OHZ
.
8.
C
= 5 pF for t
.
9.
All AC measurements are referenced to 1.5V except t
, t
, and t
OHZ
.
10. t
OE
and t
are measured at
±
100 mV from the steady state.
11.
t
is measured at +500 mV from V
and – 500 mV from V
.
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms
and capacitance as in notes 7 and 8, unless otherwise specified.
13. Access time includes all data outputs switching simultaneously.
14. At any given temperature and voltage condition, t
is greater than t
for any given device.
15. t
is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than t
after the clock, the decision of whether or not to include the opposite clock in the current
clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost
Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the
clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
Description
7C451-12
7C453-12
7C454-12
7C451-14
7C453-14
7C454-14
7C451-20
7C453-20
7C454-20
7C451-30
7C453-30
7C454-30
Unit
ns
Min.
12
Max.
Min.
14
Max.
Min.
20
Max.
Min.
30
Max.
Write Clock Cycle
Read Clock Cycle
12
14
20
30
ns
Clock HIGH
5
6.5
9
12
ns
Clock LOW
5
6.5
9
12
ns
Data Access Time
9
10
15
20
ns
Previous Output Data Hold After Read HIGH
0
0
0
0
ns
Previous Flag Hold After Read/Write HIGH
0
0
0
0
ns
Data Set-Up
4
5
6
7
ns
Data Hold
0
0
0
0
ns
Enable Set-Up
4
5
6
7
ns
Enable Hold
0
0
0
0
ns
OE LOW to Output Data Valid
9
10
15
20
ns
OE LOW to Output Data in Low Z
0
0
0
0
ns
OE HIGH to Output Data in High Z
9
10
15
20
ns
Read HIGH to Parity Generation
9
10
15
20
ns
Read HIGH to Parity Error Flag
9
10
15
20
ns
Flag Delay
9
10
15
20
ns
Opposite Clock After Clock
0
0
0
0
ns
3.0V
5V
OUTPUT
R1500
R2
333
C
L
INCLUDING
JIG AND
SCOPE
THé VENIN EQUIVALENT
GND
90%
10%
90%
10%
< 3 ns
< 3 ns
OUTPUT
2V
Equivalentto:
C451-4
200
ALL INPUT PULSES
C451-5
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| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
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