- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379094 > CY7C451 (Cypress Semiconductor Corp.) 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時的先進(jìn)先出) PDF資料下載
參數(shù)資料
| 型號： | CY7C451 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時的先進(jìn)先出) |
| 中文描述： | 512x9級聯(lián)與時鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的512x9可級聯(lián)定時的先進(jìn)先出） |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C451 |
CY7C451
CY7C453
CY7C454
3
PRELIMINARY
Pin Definitions
Signal
Name
D
0 – 8
I/O
I
Description
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
0 – 8
) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW then data is written into the FIFO’s
programming register. D
8
is ignored if the device is configured for parity generation.
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
0 – 7
)
out of the FIFO’s memory. If MR is active at the rising edge of CKR then data is read from the
programming register.
Function varies according to mode:
Parity disabled - same function as Q
0 – 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
Enable Write: enables the CKW input (for both non-program and program modes)
Enable Read: enables the CKR input (for both non-program and program modes)
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
Half Full Flag - synchronized to CKW.
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
Not Cascaded - XI is tied to V
SS
Cascaded - Expansion Input, connected to XO of previous device
First Load/ Retransmit Pin:
Cascaded - the first device in the daisy chain will have FL tied to V
SS
; all other devices will have FL
tied to V
CC
(Figure 2)
Not Cascaded - tied to V
CC;
Retransmit function is also available in stand alone mode by strobing RT
Master Reset: resets device to empty condition.
Non-Programming Mode: program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D
0 – 8
is written into the programmable register on the rising
edge of CKW. Program register contents appear on Q
0 – 8
after the rising edge of CKR.
Output Enable for Q
0 – 7
and Q
8
/PG/PE pins
Q
0 – 7
O
Q
8
/PG/PE
O
ENW
ENR
CKW
I
I
I
CKR
I
HF
E/F
PAFE/XO
O
O
O
XI
I
FL/RT
I
MR
I
OE
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級聯(lián)的 64K x9 先進(jìn)先出) |
| CY7C460A | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JI | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C451-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C451-30LMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C453 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-14JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。