- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379094 > CY7C451 (Cypress Semiconductor Corp.) 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時(shí)的先進(jìn)先出) PDF資料下載
參數(shù)資料
| 型號： | CY7C451 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級聯(lián)定時(shí)的先進(jìn)先出) |
| 中文描述： | 512x9級聯(lián)與時(shí)鐘FIFO的可編程標(biāo)志（帶可編程標(biāo)記的512x9可級聯(lián)定時(shí)的先進(jìn)先出） |
| 文件頁數(shù)： | 19/23頁 |
| 文件大?。?/td> | 437K |
| 代理商： | CY7C451 |
CY7C451
CY7C453
CY7C454
19
PRELIMINARY
Parity Disabled (Q8 mode)
When parity is disabled (or user does not program parity op-
tion) the CY7C451/453/454 stores all 9 bits present on D
0
8
inputs internally and will output all 9 bits on Q
0
8
Parity
Generate (PG mode)
This mode is used to generate either even or odd parity (as
programmed) from D
0
7
. D8 input is ignored. The parity bit
is stored internally as D8 and during a subsequent read will
be available on the PG pin along with the data word from
which the parity was generated (Q
0
7
). For example, if
parity generate is set to ODD and the D
0
7
inputs have an
EVEN number of 1s, PG will be HIGH.
Parity Check (PE mode)
If the CY7C451/453/454 is programmed for parity checking,
the FIFO will compare the parity of D
0
8
with the program
register. If the expected parity is present, D8 will be set
HIGH internally. When this word is later read, PE will be
HIGH. If a parity error occurs, D8 will be set LOW internally.
When this word is later read, PE will be LOW. For example,
if parity check is set to odd and D
0
8
have an even number
of 1s, a parity error occurs. When that word is later read,
PE will be asserted (LOW).
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last MR cycle. A LOW pulse on RT
resets the internal read pointer to the first physical location of the
FIFO. WCLK and RCLK may be free running but must be disabled
during and t
RTR
after the retransmit pulse. With every valid read cycle
after retransmit, previously accessed data is read and the read point-
er is incremented until it is equal to the write pointer. Flags are gov-
erned by the relative locations of the read and write pointers and are
updated during a retransmit cycle. Data written to the FIFO after ac-
tivation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Modes
During width expansion all flags (programmable and nonpro-
grammable) are available. The CY7C451/453/454 can be ex-
panded in width to provide word width greater than nine in
increments of nine. During width expansion mode all control
line inputs are common. When the FIFO is being read near the
Empty (Full) boundary, it is important to note that both sets of
flags should be checked to see if they have been updated to
the Not Empty (Not Full) condition to insure that the next read
(write) will perform the same operation on all devices.
Checking all sets of flags is critical so that data is not read from
the FIFOs “staggered” by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than t
SKEW2
after the
first write to two width-expanded devices, A and B, device
A may go Almost Empty (read recognized as flag update)
while device B stays Empty (read ignored). This occurs
because a read can be either recognized or ignored if it
occurs within t
SKEW2
of a write. The next read cycle outputs
the first half of the first word on device A while device B
updates its flags to Almost Empty. Subsequent reads will
continue to output “staggered” data assuming more data
has been written to the FIFOs.
Depth Expansion Mode
The CY7C451/453/454 can operate up to 83.3 MHz when cas-
caded. Depth expansion is accomplished by connecting ex-
pansion out (XO) of the first device to expansion in (XI) of
the next device, with XO of the last device connected to XI
of the first device. The first device has its first load pin (FL)
tied to VSS while all other devices must have this pin tied
to VCC. The first device will be the first to be write and read
enabled after a master reset.
Proper operation also requires that all cascaded devices have
common CKW, CKR, ENW, ENR, D
0
8
, Q
0
8
, and MR pins.
When cascaded, one device at a time will be read enabled
so as to avoid bus contention. By asserting XO when ap-
propriate, the currently enabled FIFO alerts the next FIFO
that it should be enabled. The next rising edge on CKR puts
Q
0
8
outputs of the first device into a high-impedance
state. This occurs regardless of the state of ENR or the next
FIFO’s Empty flag. Therefore, if the next FIFO is empty or
undergoing a latent cycle, the Q
0
8
bus will be in a high-im-
pedance state until the next device receives its first read,
which brings its data to the Q
0
8
bus.
Program Write/Read of Cascaded Devices
Programming of cascaded FIFOs is the same as for a single
device. Because the controls of the FIFOs are in parallel when
cascaded, they all get programmed the same. During program
mode, only parity is programmed since Almost Full and Almost
Empty flags are not available when CY7C451/453/454 are
cascaded. Only the “first device” (FIFO with FL=LOW) will
output its program register contents on Q
0
8
during a pro-
gram read. Q
0
8
of all other devices will remain in a
high-impedance state to avoid bus contention.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C454 | 4Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的4Kx9可級聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C466A | Asynchronous, Cascadable 64K x9 FIFOs(異步，可級聯(lián)的 64K x9 先進(jìn)先出) |
| CY7C460A | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JC | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
| CY7C460A-10JI | Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C451-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C451-30LMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C453 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-14JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C453-20JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 32-Pin PLCC 制造商:Cypress Semiconductor 功能描述:FIFO, 2K x 9, Synchronous, 32 Pin, Plastic, PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。