參數(shù)資料
型號(hào): CY7C439
廠商: Cypress Semiconductor Corp.
英文描述: Bidirectional 2K x 9 FIFO( 2K x 9雙向 先進(jìn)先出)
中文描述: 雙向2K × 9的FIFO(2K × 9雙向先進(jìn)先出)
文件頁(yè)數(shù): 2/17頁(yè)
文件大?。?/td> 282K
代理商: CY7C439
CY7C439
2
Functional Description
(continued)
bypass register provides a means of sending a 9-bit status or
control word to the FIFO-write port. The bypass data available
pin (BDA) indicates whether the bypass register is full or emp-
ty. The direction of the bypass register is always opposite to
that of the main FIFO.
The port designated to write to the bypass register drives its
bypass control pin (BYPX) LOW. The other port detects the
presence of data by monitoring BDA and reads the data by
driving its bypass control pin (BYPX) LOW. Registered bypass
operations require that the associated FIFO strobe pin (STBX)
remains HIGH. Registered bypass operations do not affect
data residing in the FIFO, or FIFO operations at the other port.
Transparent bypass provides a means of transferring a single
word (9 bits) of data immediately in either direction. This fea-
ture allows the device to act as a simple 9-bit bidirectional buff-
er. This is useful for allowing the controlling circuitry to access
a dumb peripheral for control/programming information.
For transparent bypass, the port wishing to send immediate
data to the other side drives both its bypass and its strobe pins
LOW simultaneously. This causes the buffered data to be driv-
en out of the other port. On-chip circuitry detects conflicting
use of the control pins and causes both data ports to enter a
high-impedance state until the conflict is resolved.
Additionally, a Test mode is offered on the CY7C439. This
mode allows the user to load data into the FIFO and then read
it back out of the same port. Built-In Self Test (BIST) and diag-
nostic functions can take advantage of these features.
The CY7C439 is fabricated using an advanced 0.8
μ
N-well
CMOS technology. Input ESD protection is greater than 2000V
and latch-up is prevented by reliable layout techniques, guard
rings, and a substrate bias generator.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
......................................
65
°
C to+150
°
C
Ambient Temperature with
Power Applied
...................................................
55
°
C to+125
°
C
Supply Voltage to Ground Potential
..................
0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State
......................................................
0.5V to+7.0V
DC Input Voltage
.................................................
3.0V to +7.0V
Power Dissipation..........................................................1.0W
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
Selection Guide
7C439-25
28.5
25
147
7C439-30
25
30
140
170
7C439-40
20
40
130
160
7C439-65
12.5
65
115
145
Frequency (MHz)
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Military
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
55
°
C to +125
°
C
V
CC
Commercial
Military
[1]
5V
±
10%
5V
±
10%
Notes:
1.
T
A
is the “instant on” case temperature.
Pin Definitions
Signal
Name
A
(8-0)
B
(8-0)
BYPA
BYPB
BDA
STBA
STBB
E/F
HF
MR
I/O
I/O
I/O
I
I
O
I
I
O
O
I
Description
Data Port Associated with BYPA and STBA
Data Port Associated with BYPB and STBB
Registered Bypass Mode Select for A Side
Registered Bypass Mode Select for B Side
Bypass Data Available Flag
Data Strobe for A Side
Data Strobe for B Side
Encoded Empty/Full Flag
Half Full Flag
Master Reset
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