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參數(shù)資料
| 型號(hào)： | CY7C439 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Bidirectional 2K x 9 FIFO( 2K x 9雙向 先進(jìn)先出) |
| 中文描述： | 雙向2K × 9的FIFO（2K × 9雙向先進(jìn)先出） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 282K |
| 代理商： | CY7C439 |
CY7C439
10
Architecture
The CY7C439 consists of a 2048 by 9-bit dual-ported RAM
array, a read pointer, a write pointer, data switching circuitry,
buffers, a bypass register, control signals (STBA, STBB, BYPA,
BYPB, MR), and flags (E/F, HF, BDA).
Operation at Power-On
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. During an MR cycle, the user can initialize the device by
choosing the direction of FIFO operation (see Table 1). There is a
minimum LOW period for MR, but no maximum time. The state of
BYPA is latched internally by the rising edge of MR and used to de-
termine the direction of subsequent data operations.
Resetting the FIFO
During the reset condition (see Table 1), the FIFO three-states
the data ports, sets BDA and HF HIGH, E/F LOW, and ignores the
state of BYPA/B and STBA/B. The bypass registers are initialized to
zero. During this time the user is expected to set the direction of the
FIFO by driving BYPA HIGH or LOW, and BYPB, STBA, and STBB
HIGH. If BYPA is LOW (selecting direction B>A), the FIFO will then
remain in a reset condition until the user terminates the reset opera-
tion by driving BYPA HIGH. If BYPA is HIGH (selecting direction A>B),
the reset condition terminates after the rising edge of MR. The entire
reset phase can be accomplished in one cycle time of tRC.
FIFO Operation
The operation of the FIFO requires only one control pin per
port (STBX). The user determines the direction of the FIFO data flow
by initiating an MR cycle (see Table 1), which clears the FIFO and
bypass register and sets the data path and control signal multiplexers.
The bypass register is configured in the opposite direction to the FIFO
data flow. The FIFO direction can be reversed at any time by initiating
another MR cycle. Data is written into the FIFO on the rising edge of
the input, STBX, and read from the FIFO by a low level at the output,
STBX. The two ports are asynchronous and independent. If the user
attempts to read the FIFO when it is empty, no action takes place (the
read pointer is not incremented) until the other port writes to the FIFO.
Then a bubble-through read takes place, in which the read strobe is
generated internally and the data becomes available at the read port
shortly thereafter if the read strobe (STBX) is still LOW. Similarly, for
an attempted write operation when the FIFO is full, no internal oper-
ation takes place until the other port performs a read operation, at
Switching Waveforms
(Continued)
C439-16
Test ModeTimingDiagram
t
MRSC
t
PMR
t
RMR
t
RPS
t
RPBS
t
RPBH
t
RMR
MR
STBA/STBB
BYPA/BYPB
t
BDH
C439-17
VALID OUTPUT
VALID OUTPUT
HIGH Z
t
ESD
t
EBD
t
EDS
t
EDB
STBA
BYPA
STBB
BYPB
DATA B
ExceptionConditionTiming Diagram
[14]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C4421-10JXC | 功能描述:IC SYNC FIFO 64KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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