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參數(shù)資料
| 型號(hào)： | CY7C439 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Bidirectional 2K x 9 FIFO( 2K x 9雙向 先進(jìn)先出) |
| 中文描述： | 雙向2K × 9的FIFO（2K × 9雙向先進(jìn)先出） |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 282K |
| 代理商： | CY7C439 |
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CY7C439
11
which time the bubble-through write is performed if the write strobe
(STBX) is still LOW.
Registered Bypass Operation
The registered bypass feature provides a means of transfer-
ring one 9-bit word of data in the opposite direction to normal
data flow without affecting either the FIFO contents or the
FIFO write operations at the other port. The bypass register is
configured during reset to provide a data path in the opposite
direction to that of the FIFO (see Table 1). For example, if port A
is writing data to the FIFO (hence port B is reading data from the
FIFO) then BYPB is used to write to the bypass register at port B, and
BYPA is used to read a single word from the bypass register at port
A. The bypass data available flag (BDA) is generated to notify port A
that bypass data is available. BDA goes true on the trailing edge of
the BYPX write operation and false upon the trailing edge of the
BYPX read operation.
Data is written on the rising edge of BYPX into the bypass register
for later retrieval by the other port, regardless of the state of BDA. The
bypass register is read by a low level at BYPX, regardless of the state
of BDA.
Transparent Bypass Operation
The transparent bypass feature provides a means of sending
immediate data “around” the FIFO in either direction. The
FIFO contents are not affected by the use of transparent by-
pass, but the control signals for transparent bypass are shared
with those of the normal FIFO operation. Hence there are lim-
itations on the use of transparent bypass to ensure that data
integrity and ease of use are preserved. The port wishing to
send immediate data must ensure that the other port will not
attempt a FIFO read or write during the transparent bypass
cycle. If this is not possible, registered bypass or external cir-
cuitry should be used.
Transparent bypass mode is initiated by bringing both BYPA
and STBA LOW together. Care should be taken to observe the fol-
lowing constraints on the timing relationships. Since STBA is used for
normal FIFO operations, it must follow BYPA falling edge by tTBS to
prevent erroneous FIFO read or write operations. Since BYPA is used
alone to initiate registered bypass read and write, it is internally de-
layed before initiating registered bypass. If STBA falls during this time,
delay registered bypass is averted, and transparent bypass is initiat-
ed. Identical arguments apply to BYPB and STBB.
If a transparent bypass sequence is successfully accom-
plished, data presented to the initiating port (port A in the
above discussion) will be buffered to the other (port B) after
tDL. Either port can initiate a transparent bypass operation at any
time, but if the control signals (STBA/B, BYPA/B) are in conflict (ex-
ception condition), internal circuitry will switch both ports to high-im-
pedance until the conflict is resolved.
Test Mode Operation
The Test mode feature provides a means of reading the FIFO
contents from the same port that the data was written to the
FIFO. This feature is useful for Built-In Self Test (BIST) and
diagnostic functions. To utilize this capability, initialize FIFO
direction A to B and load data into the FIFO using normal write
timing. In order to read data back out of the same port (port A),
initiate a MR cycle with both BYPA and BYPB LOW (see Test Mode
Timing diagram). After completing the cycle, the data can be read out
of port A in FIFO order. Data will be inverted when read out of the
device. Also, flags are not valid when reading data.
Flag Operation
There are two flags, Empty/Full (E/F) and Half Full (HF), which are
used to decode four FIFO states (see Table 4). The states are empty,
1-1024 locations full, 1025-2047 locations full, and full. Note that two
conditions cause the E/F pin to go LOW, Empty and Full, hence both
flag pins must be used to resolve the two conditions.
.
Table 1. FIFO Direction Select Truth
MR
BYPA
BYPB
STBA
STBB
Action
1
X
X
X
X
Normal Operation
1
1
1
1
FIFO Direction A to B, Registered Bypass Direction B to A
0
1
1
1
FIFO Direction B to A, Registered Bypass Direction A to B
0
X
X
X
X
Reset Condition
Table 2. Bypass Operation Truth Table
Direction
STBA
BYPA
STBB
BYPB
Action
A
á
B
1
1
Normal FIFO Operations, Write at A, Read at B
A
á
B
1
1
Normal FIFO Read at B, Bypass Register Read at A
A
á
B
1
1
Normal FIFO Write at A, Bypass Register Write at B
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