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參數(shù)資料
| 型號： | CY7C43636 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出) |
| 中文描述： | 512 x36/x18x2三總線的FIFO（512 x36/x18x2三路總線先進先出） |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 577K |
| 代理商： | CY7C43636 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
9
PRELIMINARY
t
REF
Propagation Delay Time, CLKA
↑
to EFA/ORA and
CLKB
↑
to EFB/ORB
Propagation Delay Time, CLKA
↑
to AEA and CLKB
↑
to AEB
Propagation Delay Time, CLKA
↑
to AFA and CLKC
↑
to AFC
Propagation Delay Time, CLKA
↑
to MBF1 LOW or
MBF2 HIGH and CLKB
↑
to MBF2 LOW or MBF1
HIGH
Propagation Delay Time, CLKA
↑
to B
0
–
17[9]
and
CLKB
↑
to A
0
–
35[10]
Propagation Delay Time, MBA to A
0
–
35
Valid and
MBB to B
0
–
17
Valid
Propagation Delay Time, MRS1 or PRS1 LOW to
AEB LOW, AFA HIGH, FFA/IRA LOW, EFB/ORB
LOW and MBF1 HIGH and MRS2 or PRS2 LOW to
AEA LOW, AFC HIGH, FFC/IRC LOW, EFA/ORA
LOW and MBF2 HIGH
1
6
1
8
1
8
ns
t
PAE
1
6
1
8
1
8
ns
t
PAF
1
6
1
8
1
8
ns
t
PMF
0
6
0
8
0
12
ns
t
PMR
1
7
2
11
3
12
ns
t
MDV
1
6
2
9
3
11
ns
t
RSF
1
6
1
10
1
15
ns
t
EN
Enable Time, CSA or W/RA LOW to A
0
–
35
Active and
CSB LOW and RENB HIGH to B
0
–
17
Active
Disable Time, CSA or W/RA HIGH to A
0
–
35
at High
Impedance and CSB HIGH or RENB LOW to B
0
–
17
at High Impedance
1
5
2
8
2
10
ns
t
DIS
t
PRT
t
RTR
Notes:
9.
10. Writing data to the Mail2 register when the A
0
–
35
outputs are active and MBA is HIGH.
1
5
1
6
1
8
ns
Retransmit Pulse Width
60
60
60
ns
Retransmit recovery Time
90
90
90
ns
Writing data to the Mail1 register when the B
0
–
17
outputs are active and MBB is HIGH.
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
7C43626/
36/46/66/86
-7
7C43626/
36/46/66/86
-10
7C43626/
36/46/66/86
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出) |
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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