參數(shù)資料
型號: CY7C43636
廠商: Cypress Semiconductor Corp.
英文描述: 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出)
中文描述: 512 x36/x18x2三總線的FIFO(512 x36/x18x2三路總線先進先出)
文件頁數(shù): 14/40頁
文件大小: 577K
代理商: CY7C43636
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
14
PRELIMINARY
Notes:
19. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
20. t
is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
, then FFC/IRC may transition HIGH one cycle later than show.
21. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Switching Waveforms
(continued)
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
t
FSS
t
SPH
t
SENS
t
SENH
t
SENH
t
SENS
t
SDH
t
SDS
t
SDH
t
SDS
t
SKEW1[20]
t
WFF
AFA Offset (Y1) MSB
t
FSS
t
FSH
t
WFF
CLKA
MRS1, MRS2
SPM
FFA/IRA
FS1/SEN
CLKB
FFA/IRA
[19]
FS0/SD
[21]
AEA Offset (X2) LSB
相關PDF資料
PDF描述
CY7C43626 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出)
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出)
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出)
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