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參數(shù)資料
| 型號(hào)： | CY7C43636 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出) |
| 中文描述： | 512 x36/x18x2三總線的FIFO（512 x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 36/40頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CY7C43636 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
36
PRELIMINARY
Notes:
58. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
59. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
Table 1. Flag Programming
SPM
FS1/SEN
FS0/SD
MRS1
↑
X
↑
X
↑
X
↑
↑
↑
↑
↑
MRS2
X1 and Y1 Registers
[58]
X2 and Y2 Registers
[59]
H
H
H
X
↑
X
↑
X
↑
↑
↑
↑
↑
↑
64
X
H
H
H
X
64
H
H
L
16
X
H
H
L
X
16
H
L
H
8
X
H
L
H
X
8
H
L
L
Parallel programming via Port A
Parallel programming via Port A
L
H
L
Serial programming via SD
Serial programming via SD
L
H
H
Reserved
Reserved
L
L
H
Reserved
Reserved
L
L
L
Reserved
Reserved
Table 2. Port A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A
0
–
35
OUTPUTS
In high-impedance state
PORT FUNCTION
H
X
X
X
X
None
L
H
L
X
X
↑
↑
X
↑
X
↑
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO1 write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
Active, FIFO2 output register
None
L
L
H
L
Active, FIFO2 output register
FIFO2 read
L
L
L
H
Active, Mail2 register
None
L
L
H
H
Active, Mail2 register
Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function Table
CSB
RENB
MBB
CLKB
B
0
–
17
OUTPUTS
In high-impedance state
PORT FUNCTION
H
X
X
X
None
L
L
L
X
↑
X
↑
Active, FIFO1 output register
None
L
H
L
Active, FIFO1 output register
FIFO1 read
L
L
H
Active, Mail1 register
None
L
H
H
Active, Mail1 register
Mail1 read (set MBF1 HIGH)
Table 4. Port C Enable Function Table
WENC
MBC
CLKC
↑
↑
X
C
0
–
17
OUTPUTS
In high-impedance state
PORT FUNCTION
H
L
FIFO2 write
H
H
In high-impedance state
Mail2 write
L
L
In high-impedance state
None
L
H
X
Active, Mail1 register
None
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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