參數(shù)資料
型號(hào)： CY7C43633
廠商： Cypress Semiconductor Corp.
英文描述： 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進(jìn)先出帶總線匹配)
中文描述： 512 x36單向同步FIFO瓦特/總線匹配（512 x36單向同步先進(jìn)先出帶總線匹配）
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 422K
代理商： CY7C43633
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
4
PRELIMINARY
Pin Definitions
Signal Name
Description
I/O
Function
A
0
–
35
AE
Port A Data
I
36-bit unidirectional data port for side A.
Almost Empty
Flag (Port B)
O
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in the FIFO2 is less than or equal to the value in the Almost Empty A offset
register, X.
AF
Almost Full Flag
O
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in the FIFO is less than or equal to the value in the Almost Full A offset
register, Y.
B
0
–
35
BE/FWFT
Port B Data
O
36-bit unidirectional data port for side B.
Big Endian/
First-Word Fall-
Through Select
I
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data
flow). A LOW on BE will select Little Endian operation. In this case, the least significant
byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port
B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard Mode, a LOW selects First-Word Fall-Through Mode.
Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
BM
Bus Match
Select (Port B)
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the
state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOW-
to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all synchro-
nized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
Select
I
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0
–
35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0
–
35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A
0
–
35
outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
CSB
Port B Chip
Select
I
EF/OR
Empty/Output
Ready Flag
(Port B)
O
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
FF/IR
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function
is selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values (8, 16, or 64), parallel load from Port A,
and serial load. When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When
FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X
and Y registers. The number of bit writes required to program the offset registers is 16
for the CY7C43623, 18 for the CY7C43633, 20 for the CY7C43643, 24 for the
CY7C43663, and 28 for the CY7C43683. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
FS0/SD
Flag Offset
Select 0/Serial
Data
I
相關(guān)PDF資料
PDF描述
CY7C43623 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43643 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43663 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43683 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43634 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進(jìn)先出 帶總線匹配)
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參數(shù)描述
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CY7C43643-15AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43643AV-10AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP
CY7C43643AV-15AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP
CY7C43643AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP
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