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參數(shù)資料
| 型號(hào)： | CY7C43643 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 每1000 x36單向同步FIFO瓦特/總線匹配（每1000 x36單向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 422K |
| 代理商： | CY7C43643 |
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CY7C43623
CY7C43633/CY7C43643
CY7C43663/CY7C43683
PRELIMINARY
256/512/1K/4K/16K x36 Unidirectional
Synchronous FIFO w/ Bus Matching
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 13, 1999
Featuressor
High-speed, low-power, Unidirectional, First-in First-
out (FIFO) memories w/bus matching capabilities
256x36 (CY7C43623)
512x36 (CY7C43633)
1Kx36 (CY7C43643)
4Kx36 (CY7C43663)
16Kx36 (CY7C43683)
0.35-micron CMOS for optimum speed/power
High-speed 133-MHz operation (7.5 ns read/write cycle
times)
Low power
—I
CC
= 100 mA
—I
SB
= 10 mA
Fully asynchronous and simultaneous read and write
operation permitted
Mailbox bypass register for each FIFO
Parallel and Serial Programmable Almost Full and
Almost Empty flags
Retransmit function
Standard or FWFT mode user selectable
Partial Reset
Big or Little Endian format for word or byte bus sizes
128-pin TQFP packaging
Pin-compatible, feature enhanced, density upgrade to
IDT723623/33/43 family
Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
I
R
O
R
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
256/512/1K
4K/16Kx36
Dual Ported
Memory
Mail2
Register
FIFO,
Mail1
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
MRS2
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A
0–35
MBF2
BE/FWFT
B
0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
B
36
36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43663 | 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43683 | 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43634 | 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進(jìn)先出 帶總線匹配) |
| CY7C43624 | 256 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(256 x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43644 | 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43644AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 128-Pin TQFP |
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