參數(shù)資料
型號: CY7C43643
廠商: Cypress Semiconductor Corp.
英文描述: 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進(jìn)先出帶總線匹配)
中文描述: 每1000 x36單向同步FIFO瓦特/總線匹配(每1000 x36單向同步先進(jìn)先出帶總線匹配)
文件頁數(shù): 11/28頁
文件大小: 422K
代理商: CY7C43643
CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
11
PRELIMINARY
Notes:
15. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
16. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
17. Read from FIFO.
Switching Waveforms
(continued)
Serial Programming of the Almost Full Flag and Almost Empty Flag
Offset Values (CY Standard and FWFT Modes)
t
FSS
t
SPH
t
SENS
t
SENH
t
SENH
t
SENS
t
SDH
t
SDS
t
SDH
t
SDS
t
WFF
AF Offset (Y) MSB
t
FSS
t
FSH
CLKA
MRS1, MRS2
SPM
FF/IR
FS1/SEN
FS0/SD
[16]
AE Offset (X) LSB
OR
t
CLKH
t
CLKL
t
ENS
t
DIS
t
ENS
t
EN
t
CLK
t
DIS
t
ENH
t
ENS
t
ENH
t
A
t
A
t
A
t
A
t
EN
t
EN
t
MDV
t
MDV
W1
[17]
W2
[17]
W1
[17]
W2
[17]
W3
[17]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B
0
35
(Standard Mode)
B
0
35
(FWFT Mode)
Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)
相關(guān)PDF資料
PDF描述
CY7C43663 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43683 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(16K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43634 512 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(512 x36 x2 雙向同步先進(jìn)先出 帶總線匹配)
CY7C43624 256 x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(256 x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43644 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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