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參數(shù)資料
| 型號： | CY7C43643 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配) |
| 中文描述： | 每1000 x36單向同步FIFO瓦特/總線匹配（每1000 x36單向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 422K |
| 代理商： | CY7C43643 |
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CY7C43623
CY7C43633/CY7C43643
CY7C43663
/
CY7C43683
20
PRELIMINARY
Signal Description
Master Reset (MRS1
,
MRS2)
The FIFO memory of the CY7C436x3 undergoes a complete
reset by taking its associated Master Reset (MRS1, MRS2)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Master Reset
input can switch asynchronously to the clocks. A Master Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Master Reset, the FIFO
’
s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be performed on the FIFO after power
up, before data is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input or
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and Se-
rial Programming Mode (SPM) inputs for choosing the Almost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full flag offset programming below).
Partial Reset (PRS)
Each of the two FIFO memories of the CY7C436x3 undergoes
a limited reset by taking its associated Partial Reset (PRS)
input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset
inputs can switch asynchronously to the clocks. A Partial Rest
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Partial Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. After a Partial Reset, the FIFO
’
s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or seri-
al), and timing mode (FWFT or IDT Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First-Word Fall-Through (BE/FWFT)
This is a dual-purpose pin. At the time of Master Reset, the BE
select function is active, permitting a choice of Big or Little
Endian byte arrangement for data written to or read from Port
B. This selection determines the order by which bytes (or
words) of data are transferred through this port. For the follow-
ing illustrations, assume that a byte (or word) bus size has
been selected for Port B. (Note that when Port B is configured
for a long-word size, the Big Endian function has no application
and the BE input is a
“
Don
’
t Care.
”
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When data is moving in the direction from Port
A to Port B, the most significant byte (word) of the long-word
written to Port A will be read from Port B first; the least signif-
icant byte (word) of the long-word written to Port A will be read
from Port B last. When data is moving in the direction from Port
B to Port A, the byte (word) written to Port B first will be read
from Port A as the most significant byte (word) of the long-
word; the byte (word) written to Port B last will be read from
Port A as the least significant byte (word) of the long-word.
A LOW on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Little Endian
arrangement. When data is moving in the direction from Port
A to Port B, the least significant byte (word) of the long-word
written to Port A will be read from Port B first; the most signif-
icant byte (word) of the long-word written to Port A will be read
from Port B last. When data is moving in the direction from Port
B to Port A, the byte (word) written to Port B first will be read
from port A as the least significant byte (word) of the long-
word; the byte (word) written to Port B last will be read from
Port A as the most significant byte (word) of the long-word.
After Master Reset, the FWFT select function is active, permit-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input at the second LOW-to-HIGH transition of
CLKA will select CY Standard Mode. This mode uses the Emp-
ty Flag function (EF) to indicate whether or not there are any
words present in the FIFO memory. It uses the Full Flag func-
tion (FF) to indicate whether or not the FIFO memory has any
free space for writing. In CY Standard Mode, every word read
from the FIFO, including the first, must be requested using a
formal read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input during the next LOW-to-HIGH transition
of CLKA will select FWFT Mode. This mode uses the Output
Ready function (OR) to indicate whether or not there is valid
data at the data outputs (B
0
–
35
). It also uses the Input Ready
function (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Two registers in the CY7C436x3 are used to hold the offset
values for the Almost Empty and Almost Full flags. The Port A
Almost Empty flag (AE) offset register is labeled X. The Port B
Almost Full flag (AF) offset register is labeled Y. The index of
each register name corresponds with preset values during the
reset of a FIFO, programmed in parallel using the FIFO
’
s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see
Table 1
).
To load a FIFO
’
s Almost Empty flag and Almost Full flag offset
registers with one of the three preset values listed in
Table 1
,
the Serial Program Mode (SPM) and at least one of the flag-
select inputs must be HIGH during the LOW-to-HIGH transition
of its Master Reset input (MRS1, MRS2). For example, to load
the preset value of 64 into X and Y, SPM, FS0 and FS1 must
be HIGH when the FIFO reset (MRS1, MRS2) returns HIGH.
When using one of the preset values for the flag offsets, the
FIFO can be reset simultaneously or at different times.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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